{"id":"https://openalex.org/W4386108398","doi":"https://doi.org/10.1109/tcsii.2023.3307676","title":"FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation","display_name":"FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation","publication_year":2023,"publication_date":"2023-08-23","ids":{"openalex":"https://openalex.org/W4386108398","doi":"https://doi.org/10.1109/tcsii.2023.3307676"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2023.3307676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3307676","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100445235","display_name":"Yu Wang","orcid":"https://orcid.org/0000-0002-5561-4435"},"institutions":[{"id":"https://openalex.org/I4210128418","display_name":"Nanjing Xiaozhuang University","ror":"https://ror.org/03fnv7n42","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210128418"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yu Wang","raw_affiliation_strings":["School of Electronics Engineering, Nanjing Xiaozhuang University, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics Engineering, Nanjing Xiaozhuang University, Nanjing, China","institution_ids":["https://openalex.org/I4210128418"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020001240","display_name":"Xingcheng Liang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210166603","display_name":"Jinling Institute of Technology","ror":"https://ror.org/05em1gq62","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210166603"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xingcheng Liang","raw_affiliation_strings":["School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China","institution_ids":["https://openalex.org/I4210166603"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103270742","display_name":"Shuai Niu","orcid":"https://orcid.org/0009-0005-7774-3069"},"institutions":[{"id":"https://openalex.org/I4210166603","display_name":"Jinling Institute of Technology","ror":"https://ror.org/05em1gq62","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210166603"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuai Niu","raw_affiliation_strings":["School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China","institution_ids":["https://openalex.org/I4210166603"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100458250","display_name":"Chi Zhang","orcid":"https://orcid.org/0009-0000-3737-2682"},"institutions":[{"id":"https://openalex.org/I4210166603","display_name":"Jinling Institute of Technology","ror":"https://ror.org/05em1gq62","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210166603"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chi Zhang","raw_affiliation_strings":["School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China","institution_ids":["https://openalex.org/I4210166603"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020860781","display_name":"Fei Lyu","orcid":"https://orcid.org/0000-0003-2282-1574"},"institutions":[{"id":"https://openalex.org/I4210166603","display_name":"Jinling Institute of Technology","ror":"https://ror.org/05em1gq62","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210166603"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fei Lyu","raw_affiliation_strings":["School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information Engineering, Jinling Institute of Technology, Nanjing, China","institution_ids":["https://openalex.org/I4210166603"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063032740","display_name":"Yuanyong Luo","orcid":"https://orcid.org/0000-0002-4450-066X"},"institutions":[{"id":"https://openalex.org/I2250955327","display_name":"Huawei Technologies (China)","ror":"https://ror.org/00cmhce21","country_code":"CN","type":"company","lineage":["https://openalex.org/I2250955327"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuanyong Luo","raw_affiliation_strings":["Department of Turing Architecture Design, HiSilicon, Linx Lab, Huawei Corporation, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Department of Turing Architecture Design, HiSilicon, Linx Lab, Huawei Corporation, Shenzhen, China","institution_ids":["https://openalex.org/I2250955327"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5100445235"],"corresponding_institution_ids":["https://openalex.org/I4210128418"],"apc_list":null,"apc_paid":null,"fwci":0.1303,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4357227,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"71","issue":"1","first_page":"450","last_page":"454"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.841164231300354},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6757767200469971},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6645169258117676},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.6487905979156494},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.46604835987091064},{"id":"https://openalex.org/keywords/serial-binary-adder","display_name":"Serial binary adder","score":0.44853997230529785},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4444623291492462},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.43734613060951233},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4232845902442932},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.40934091806411743},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32202252745628357},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.19843405485153198},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12651506066322327},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11710116267204285}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.841164231300354},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6757767200469971},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6645169258117676},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.6487905979156494},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.46604835987091064},{"id":"https://openalex.org/C116206932","wikidata":"https://www.wikidata.org/wiki/Q7454686","display_name":"Serial binary adder","level":4,"score":0.44853997230529785},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4444623291492462},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.43734613060951233},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4232845902442932},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.40934091806411743},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32202252745628357},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.19843405485153198},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12651506066322327},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11710116267204285},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2023.3307676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2023.3307676","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.49000000953674316}],"awards":[{"id":"https://openalex.org/G1212163249","display_name":null,"funder_award_id":"jit-b-201907","funder_id":"https://openalex.org/F4320327505","funder_display_name":"Jinling Institute of Technology"},{"id":"https://openalex.org/G2424954739","display_name":null,"funder_award_id":"62201234","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320327505","display_name":"Jinling Institute of Technology","ror":"https://ror.org/05em1gq62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2008634303","https://openalex.org/W2052363354","https://openalex.org/W2055879113","https://openalex.org/W2098403770","https://openalex.org/W2104034455","https://openalex.org/W2106353155","https://openalex.org/W2139671924","https://openalex.org/W3035768610","https://openalex.org/W3211494732"],"related_works":["https://openalex.org/W2364181090","https://openalex.org/W4299002946","https://openalex.org/W2950518102","https://openalex.org/W2953746839","https://openalex.org/W2186469553","https://openalex.org/W2370097872","https://openalex.org/W2777618078","https://openalex.org/W1882870471","https://openalex.org/W2516396101","https://openalex.org/W4313466943"],"abstract_inverted_index":{"The":[0,10],"double-multiply":[1,39],"(DM)":[2],"operation":[3],"(x\u00d7y\u00d7z)":[4],"is":[5,92],"frequently":[6],"used":[7],"in":[8,111],"computing.":[9],"traditional":[11,118,133],"design":[12,41,123,134],"based":[13],"on":[14],"two":[15],"serial":[16],"multipliers":[17],"(without":[18],"fusion)":[19],"leads":[20],"to":[21,72,82,131],"significant":[22],"area":[23,126],"requirements":[24],"and":[25,44,62,84,127],"critical":[26],"path":[27],"delays":[28],"of":[29,58,69],"the":[30,49,53,59,77,87,95,104,112,117,132,137],"circuit.":[31],"In":[32,48,120],"this":[33],"work,":[34],"we":[35],"propose":[36],"a":[37],"fused":[38,96],"(FDM)":[40],"for":[42],"low-latency":[43],"area-and":[45],"power-efficient":[46],"implementation.":[47],"first":[50],"multiplication":[51],"operation,":[52],"modified":[54],"Booth":[55],"(MB)":[56],"encodings":[57],"carry":[60],"(C)":[61],"sum":[63],"(S)":[64],"are":[65,80],"generated":[66],"separately":[67],"instead":[68],"being":[70],"added":[71],"each":[73],"other":[74],"directly.":[75],"After":[76],"partial":[78],"products":[79],"compressed":[81],"C":[83],"S":[85],"by":[86],"carry-skip":[88],"adder":[89],"(CSA),":[90],"(C+S)\u00d7z":[91],"calculated":[93],"via":[94],"add\u2013multiply":[97],"(FAM)":[98],"technique.":[99],"Synthesized":[100],"results":[101],"show":[102],"that":[103],"proposed":[105],"hardware":[106],"achieves":[107],"an":[108],"11.54%":[109],"reduction":[110],"minimum":[113],"delay":[114],"compared":[115,130],"with":[116],"design.":[119],"addition,":[121],"our":[122],"saves":[124],"17.40%":[125],"26.86%":[128],"power":[129],"when":[135],"achieving":[136],"same":[138],"delay.":[139]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}