{"id":"https://openalex.org/W4285168734","doi":"https://doi.org/10.1109/tcsii.2022.3174622","title":"Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications","display_name":"Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications","publication_year":2022,"publication_date":"2022-05-12","ids":{"openalex":"https://openalex.org/W4285168734","doi":"https://doi.org/10.1109/tcsii.2022.3174622"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2022.3174622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2022.3174622","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047341225","display_name":"Michele Caselli","orcid":"https://orcid.org/0000-0003-3807-8033"},"institutions":[{"id":"https://openalex.org/I124601658","display_name":"University of Parma","ror":"https://ror.org/02k7wn190","country_code":"IT","type":"education","lineage":["https://openalex.org/I124601658"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Michele Caselli","raw_affiliation_strings":["Department of Engineering and Architecture, University of Parma, Parma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Engineering and Architecture, University of Parma, Parma, Italy","institution_ids":["https://openalex.org/I124601658"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082798974","display_name":"Peter Debacker","orcid":"https://orcid.org/0000-0003-3825-5554"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Peter Debacker","raw_affiliation_strings":["Compute System Architecture (CSA), imec, Leuven, Belgium"],"affiliations":[{"raw_affiliation_string":"Compute System Architecture (CSA), imec, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5032000935","display_name":"Andrea Boni","orcid":"https://orcid.org/0000-0001-7649-2871"},"institutions":[{"id":"https://openalex.org/I124601658","display_name":"University of Parma","ror":"https://ror.org/02k7wn190","country_code":"IT","type":"education","lineage":["https://openalex.org/I124601658"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Andrea Boni","raw_affiliation_strings":["Department of Engineering and Architecture, University of Parma, Parma, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Engineering and Architecture, University of Parma, Parma, Italy","institution_ids":["https://openalex.org/I124601658"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5047341225"],"corresponding_institution_ids":["https://openalex.org/I124601658"],"apc_list":null,"apc_paid":null,"fwci":0.9148,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.72603195,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"69","issue":"7","first_page":"3084","last_page":"3089"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7841231226921082},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.5541896224021912},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5482840538024902},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5438807606697083},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.5159562230110168},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5042997598648071},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.49811840057373047},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4906693696975708},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4661990702152252},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4577641785144806},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4553471505641937},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4363342225551605},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43506288528442383},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.416191041469574},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4154837727546692},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3725181221961975},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36339446902275085},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3088516592979431},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.26609739661216736},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14482393860816956},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09844952821731567},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09717825055122375}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7841231226921082},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.5541896224021912},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5482840538024902},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5438807606697083},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5159562230110168},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5042997598648071},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.49811840057373047},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4906693696975708},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4661990702152252},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4577641785144806},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4553471505641937},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4363342225551605},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43506288528442383},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.416191041469574},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4154837727546692},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3725181221961975},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36339446902275085},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3088516592979431},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26609739661216736},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14482393860816956},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09844952821731567},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09717825055122375},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2022.3174622","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2022.3174622","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W2586654419","https://openalex.org/W2894696827","https://openalex.org/W2896152043","https://openalex.org/W2904299207","https://openalex.org/W2920326572","https://openalex.org/W2951266961","https://openalex.org/W2952800885","https://openalex.org/W2965351898","https://openalex.org/W2966524683","https://openalex.org/W2974585810","https://openalex.org/W2982644126","https://openalex.org/W3000301330","https://openalex.org/W3005599125","https://openalex.org/W3005729543","https://openalex.org/W3015432327","https://openalex.org/W3015980402","https://openalex.org/W3015982917","https://openalex.org/W3026786299","https://openalex.org/W3061567197","https://openalex.org/W3083523630","https://openalex.org/W3107913576","https://openalex.org/W3120016950","https://openalex.org/W3138828421","https://openalex.org/W3138864966","https://openalex.org/W3139067602","https://openalex.org/W3155456425","https://openalex.org/W3159274266","https://openalex.org/W3161810489","https://openalex.org/W3174733244","https://openalex.org/W3174812964","https://openalex.org/W3175426148","https://openalex.org/W3192589754","https://openalex.org/W4205807340","https://openalex.org/W4220837341","https://openalex.org/W4312585333","https://openalex.org/W6764214684","https://openalex.org/W6800087528","https://openalex.org/W6800934724"],"related_works":["https://openalex.org/W2007222089","https://openalex.org/W4242258007","https://openalex.org/W2155285526","https://openalex.org/W2394022884","https://openalex.org/W2185815555","https://openalex.org/W2071235072","https://openalex.org/W1924227955","https://openalex.org/W4242038055","https://openalex.org/W1493881961","https://openalex.org/W2128579103"],"abstract_inverted_index":{"This":[0],"tutorial":[1],"focuses":[2],"on":[3,101],"memory":[4,47,70],"elements":[5],"and":[6,35,76],"analog/digital":[7],"(A/D)":[8],"interfaces":[9],"used":[10],"in":[11,19],"mixed-signal":[12],"accelerators":[13],"for":[14,58,72,93],"deep":[15],"neural":[16],"networks":[17],"(DNNs)":[18],"machine":[20],"learning":[21],"(ML)":[22],"applications.":[23],"These":[24],"very":[25],"dedicated":[26],"systems":[27],"exploit":[28],"analog":[29],"in-memory":[30],"computation":[31,80],"(AiMC)":[32],"of":[33,45,63,96,105],"weights":[34,51],"input":[36],"activations":[37],"to":[38],"accelerate":[39],"the":[40,46,50,53,60,64,83,94,97,102,106,111],"DNN":[41],"algorithm.":[42],"The":[43],"co-optimization":[44],"cell":[48],"storing":[49],"with":[52,78],"peripheral":[54],"circuits":[55],"is":[56],"mandatory":[57],"improving":[59],"performance":[61],"metrics":[62],"accelerator.":[65],"In":[66],"this":[67],"tutorial,":[68],"four":[69],"devices":[71],"AiMC":[73,98],"are":[74],"reported":[75],"analyzed":[77],"their":[79],"scheme,":[81],"including":[82],"digital-to-analog":[84],"converter":[85],"(DAC).":[86],"Moreover,":[87],"we":[88],"review":[89],"analog-to-digital":[90],"converters":[91],"(ADCs)":[92],"quantization":[95],"results,":[99],"focusing":[100],"design":[103],"trade-offs":[104],"different":[107],"topologies":[108],"given":[109],"by":[110],"context.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
