{"id":"https://openalex.org/W3196491533","doi":"https://doi.org/10.1109/tcsii.2021.3107684","title":"A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application","display_name":"A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application","publication_year":2021,"publication_date":"2021-08-30","ids":{"openalex":"https://openalex.org/W3196491533","doi":"https://doi.org/10.1109/tcsii.2021.3107684","mag":"3196491533"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2021.3107684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3107684","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049567005","display_name":"Alok Kumar Mishra","orcid":"https://orcid.org/0000-0001-7268-3988"},"institutions":[{"id":"https://openalex.org/I44635919","display_name":"National Institute of Technology Delhi","ror":"https://ror.org/032twef21","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I44635919"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Alok Kumar Mishra","raw_affiliation_strings":["Department of ECE, National Institute of Technology Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, National Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I44635919"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044683174","display_name":"Urvashi Chopra","orcid":"https://orcid.org/0000-0002-0584-7396"},"institutions":[{"id":"https://openalex.org/I44635919","display_name":"National Institute of Technology Delhi","ror":"https://ror.org/032twef21","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I44635919"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Urvashi Chopra","raw_affiliation_strings":["Department of ECE, National Institute of Technology Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, National Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I44635919"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063015221","display_name":"Dhandapani Vaithiyanathan","orcid":"https://orcid.org/0000-0001-5235-2620"},"institutions":[{"id":"https://openalex.org/I44635919","display_name":"National Institute of Technology Delhi","ror":"https://ror.org/032twef21","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I44635919"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"D. Vaithiyanathan","raw_affiliation_strings":["Department of ECE, National Institute of Technology Delhi, New Delhi, India"],"affiliations":[{"raw_affiliation_string":"Department of ECE, National Institute of Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I44635919"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5049567005"],"corresponding_institution_ids":["https://openalex.org/I44635919"],"apc_list":null,"apc_paid":null,"fwci":3.4406,"has_fulltext":false,"cited_by_count":51,"citation_normalized_percentile":{"value":0.93110931,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":100},"biblio":{"volume":"69","issue":"3","first_page":"1592","last_page":"1596"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8191092014312744},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.7009109854698181},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5445485711097717},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5388924479484558},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.48367080092430115},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.46764206886291504},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4648313522338867},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.4230394661426544},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41935163736343384},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4188210964202881},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4142778515815735},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3642597496509552},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3283742070198059},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.29124873876571655},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2777269780635834},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2292627990245819},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2120114266872406}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8191092014312744},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.7009109854698181},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5445485711097717},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5388924479484558},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.48367080092430115},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.46764206886291504},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4648313522338867},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.4230394661426544},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41935163736343384},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4188210964202881},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4142778515815735},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3642597496509552},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3283742070198059},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.29124873876571655},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2777269780635834},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2292627990245819},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2120114266872406},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2021.3107684","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3107684","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1966288395","https://openalex.org/W2046641314","https://openalex.org/W2047694997","https://openalex.org/W2109195618","https://openalex.org/W2145876393","https://openalex.org/W2170265438","https://openalex.org/W2741248434","https://openalex.org/W2778408213","https://openalex.org/W2796562513","https://openalex.org/W2898386872","https://openalex.org/W4236385981","https://openalex.org/W4237249613","https://openalex.org/W4253764540"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2733322820","https://openalex.org/W2020161494","https://openalex.org/W2045056374","https://openalex.org/W2298981088","https://openalex.org/W2350494013","https://openalex.org/W2472096053","https://openalex.org/W4298048893","https://openalex.org/W1965850601","https://openalex.org/W2546023602"],"abstract_inverted_index":{"In":[0],"this":[1,36],"brief,":[2],"an":[3],"extremely":[4],"low":[5,76,79,87],"power":[6,129],"true":[7],"<inline-formula":[8],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[9],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[10],"<tex-math":[11],"notation=\"LaTeX\">$1-\\phi":[12],"$":[13],"</tex-math></inline-formula>":[14],"clocking":[15],"flip-flop":[16,24,171],"is":[17,25,97,200],"proposed":[18,95,114,170,187],"using":[19,58,99],"eighteen":[20],"transistors":[21,54],"only.":[22],"The":[23,50,94,113,143,186],"a":[26,78,174,193],"synchronous":[27],"bistable":[28],"element":[29],"that":[30,81],"stores":[31],"single-bit":[32],"information.":[33],"To":[34],"design":[35],"Master":[37],"Slave":[38],"(MS)":[39],"type":[40],"architecture,":[41],"topological,":[42],"logical,":[43],"and":[44,68,86,102,139],"adaptive":[45],"coupling":[46],"techniques":[47],"are":[48,55],"employed.":[49],"minimum":[51,175],"number":[52,161],"of":[53,63,111,128,162,168,176,182],"maintained":[56],"by":[57,89,173],"above":[59],"techniques,":[60],"which":[61],"comprises":[62],"complementary":[64,70],"pass":[65],"transistor":[66,92],"logic":[67,109,116],"static":[69],"MOS":[71],"logic.":[72],"It":[73,134,199],"also":[74,135,201],"offers":[75],"power,":[77],"delay":[80,138],"speeds":[82],"up":[83],"the":[84,91,105,120,137,160,165,169,183],"flip-flops,":[85],"complexity":[88],"reducing":[90,159],"count.":[93],"circuit":[96,188],"implemented":[98],"Cadence":[100],"Virtuoso":[101],"compared":[103,131,202],"with":[104,203],"five":[106],"other":[107],"reported":[108,204],"structures":[110],"flip-flops.":[112],"hybrid":[115],"architecture":[117],"has":[118,147],"showed":[119],"highest":[121],"percentage,":[122],"i.e.,":[123],"49.73%":[124],"improvement":[125],"in":[126,178],"terms":[127],"as":[130],"to":[132,152,180],"LRFF.":[133],"improved":[136],"energy":[140],"efficiency":[141],"(EDP).":[142],"Monte":[144],"Carlo":[145],"simulation":[146],"been":[148],"performed":[149],"for":[150,155],"C":[151],"Q":[153],"Delay":[154],"20K":[156],"samples.":[157],"By":[158],"PMOS":[163],"transistors,":[164],"total":[166],"area":[167],"reduces":[172],"9.49%":[177],"comparison":[179],"state":[181],"art":[184],"work.":[185],"can":[189],"work":[190],"properly":[191],"within":[192],"frequency":[194],"range":[195],"upto":[196],"1":[197],"GHz.":[198],"18T":[205],"TSPC":[206],"flip-flop.":[207]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":15},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
