{"id":"https://openalex.org/W3185796949","doi":"https://doi.org/10.1109/tcsii.2021.3096885","title":"A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability","display_name":"A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability","publication_year":2021,"publication_date":"2021-07-13","ids":{"openalex":"https://openalex.org/W3185796949","doi":"https://doi.org/10.1109/tcsii.2021.3096885","mag":"3185796949"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2021.3096885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3096885","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://research.tue.nl/en/publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014090281","display_name":"Xugang Cao","orcid":"https://orcid.org/0000-0002-9649-0184"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xugang Cao","raw_affiliation_strings":["School of Electronic and Computer Engineering, Shenzhen Graduate School, Peking University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"School of Electronic and Computer Engineering, Shenzhen Graduate School, Peking University, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042636120","display_name":"Hailong Jiao","orcid":"https://orcid.org/0000-0002-2815-6168"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["CN","NL"],"is_corresponding":false,"raw_author_name":"Hailong Jiao","raw_affiliation_strings":["Electronic Systems Group, Eindhoven University of Technology, Eindhoven, The Netherlands","School of Electronic and Computer Engineering, Shenzhen Graduate School, Peking University, Shenzhen, China"],"affiliations":[{"raw_affiliation_string":"Electronic Systems Group, Eindhoven University of Technology, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"School of Electronic and Computer Engineering, Shenzhen Graduate School, Peking University, Shenzhen, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044629739","display_name":"Erik Jan Marinissen","orcid":"https://orcid.org/0000-0002-5058-8303"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["BE","NL"],"is_corresponding":false,"raw_author_name":"Erik Jan Marinissen","raw_affiliation_strings":["Electronic Systems Group, Eindhoven University of Technology, Eindhoven, The Netherlands","IMEC, Leuven, Belgium"],"affiliations":[{"raw_affiliation_string":"Electronic Systems Group, Eindhoven University of Technology, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"IMEC, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5014090281"],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":2.3581,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.8877989,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"69","issue":"2","first_page":"554","last_page":"558"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/scan-chain","display_name":"Scan chain","score":0.6667667627334595},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.6606358289718628},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5570279359817505},{"id":"https://openalex.org/keywords/data-retention","display_name":"Data retention","score":0.5553377270698547},{"id":"https://openalex.org/keywords/power-gating","display_name":"Power gating","score":0.5335448384284973},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5112953186035156},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49799203872680664},{"id":"https://openalex.org/keywords/power-network-design","display_name":"Power network design","score":0.47700265049934387},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4720101058483124},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.446257621049881},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.44321349263191223},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4423029124736786},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4261326789855957},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.41100746393203735},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4085756242275238},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3992476761341095},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3952023386955261},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.29756540060043335},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28685277700424194},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2691064476966858},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.1704181730747223},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12234780192375183},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.1090204119682312},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09135141968727112},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.08171510696411133}],"concepts":[{"id":"https://openalex.org/C150012182","wikidata":"https://www.wikidata.org/wiki/Q225990","display_name":"Scan chain","level":3,"score":0.6667667627334595},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.6606358289718628},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5570279359817505},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.5553377270698547},{"id":"https://openalex.org/C2780700455","wikidata":"https://www.wikidata.org/wiki/Q7236515","display_name":"Power gating","level":4,"score":0.5335448384284973},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5112953186035156},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49799203872680664},{"id":"https://openalex.org/C164565468","wikidata":"https://www.wikidata.org/wiki/Q7236535","display_name":"Power network design","level":3,"score":0.47700265049934387},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4720101058483124},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.446257621049881},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.44321349263191223},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4423029124736786},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4261326789855957},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.41100746393203735},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4085756242275238},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3992476761341095},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3952023386955261},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.29756540060043335},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28685277700424194},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2691064476966858},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.1704181730747223},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12234780192375183},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.1090204119682312},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09135141968727112},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.08171510696411133},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tcsii.2021.3096885","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3096885","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:pure.tue.nl:openaire/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Cao, X, Jiao, H & Marinissen, E J 2022, 'A Bypassable Scan Flip-Flop for Low Power Testing with Data Retention Capability', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, 9481937, pp. 554-558. https://doi.org/10.1109/TCSII.2021.3096885","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:pure.tue.nl:publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","is_oa":true,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=85110794351&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Cao, X, Jiao, H & Marinissen, E J 2022, 'A Bypassable Scan Flip-Flop for Low Power Testing with Data Retention Capability', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, 9481937, pp. 554-558. https://doi.org/10.1109/TCSII.2021.3096885","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:tue:oai:pure.tue.nl:publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","is_oa":true,"landing_page_url":"https://research.tue.nl/nl/publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","pdf_url":null,"source":{"id":"https://openalex.org/S4306401843","display_name":"Data Archiving and Networked Services (DANS)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1322597698","host_organization_name":"Royal Netherlands Academy of Arts and Sciences","host_organization_lineage":["https://openalex.org/I1322597698"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs, 69(2):9481937, 554 - 558. Institute of Electrical and Electronics Engineers","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:pure.tue.nl:openaire/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","is_oa":true,"landing_page_url":"https://research.tue.nl/en/publications/0d56ec80-1d66-4c45-9465-444dfc6ee7f9","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Cao, X, Jiao, H & Marinissen, E J 2022, 'A Bypassable Scan Flip-Flop for Low Power Testing with Data Retention Capability', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 2, 9481937, pp. 554-558. https://doi.org/10.1109/TCSII.2021.3096885","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[{"id":"https://openalex.org/G1121271761","display_name":null,"funder_award_id":"Program","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G1231421488","display_name":null,"funder_award_id":"under","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2087396116","display_name":null,"funder_award_id":"China","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2981938667","display_name":null,"funder_award_id":"Shenzhen","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3162017210","display_name":null,"funder_award_id":"201803","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3317480652","display_name":null,"funder_award_id":"Science","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3428650329","display_name":null,"funder_award_id":"KQJSCX20180323174729052","funder_id":"https://openalex.org/F4320326705","funder_display_name":"Science, Technology and Innovation Commission of Shenzhen Municipality"},{"id":"https://openalex.org/G391238517","display_name":null,"funder_award_id":", and","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G4597272072","display_name":null,"funder_award_id":"2018032","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G5994120800","display_name":null,"funder_award_id":"Natural","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6781766220","display_name":null,"funder_award_id":"62074005","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320326705","display_name":"Science, Technology and Innovation Commission of Shenzhen Municipality","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W2025698297","https://openalex.org/W2084381554","https://openalex.org/W2112564358","https://openalex.org/W2114018023","https://openalex.org/W2124276471","https://openalex.org/W2126641963","https://openalex.org/W2154950819","https://openalex.org/W2170530584","https://openalex.org/W2296084212","https://openalex.org/W2492599081","https://openalex.org/W2782250263","https://openalex.org/W3037906668","https://openalex.org/W3090268737"],"related_works":["https://openalex.org/W2152979262","https://openalex.org/W2546524276","https://openalex.org/W4226239708","https://openalex.org/W4253462032","https://openalex.org/W2117891373","https://openalex.org/W2789883751","https://openalex.org/W2145376025","https://openalex.org/W3127845477","https://openalex.org/W2147986372","https://openalex.org/W2003272148"],"abstract_inverted_index":{"The":[0,57,64,121,165,193],"power":[1,16,118,154,208,216],"consumption":[2,119],"of":[3,34,66,96,161],"modern":[4],"highly":[5],"complex":[6],"chips":[7],"during":[8,18,89,111,219],"scan":[9,90,112,220,230],"test":[10,87,117,176,221],"is":[11,51,83,109,143,186,196,217],"significantly":[12],"higher":[13],"than":[14],"the":[15,35,67,73,78,94,97,101,106,116,132,135,140,149,158,162,170,175,180,190,223,228],"consumed":[17],"functional":[19],"mode.":[20],"This":[21],"leads":[22,126],"to":[23,72,85,127,179,198,227],"substantial":[24],"heat":[25],"dissipation,":[26],"excessive":[27],"IR":[28,129],"drop,":[29],"and":[30],"unrealistic":[31],"timing":[32],"failures":[33],"integrated":[36],"circuits":[37,108],"(ICs)":[38],"under":[39],"test.":[40,56,91],"In":[41],"this":[42],"brief,":[43],"a":[44,204],"ByPassable":[45],"Scan":[46],"Data":[47],"Retention":[48],"Flip-Flop":[49],"(BPS-DRFF)":[50],"proposed":[52,58,166,194,224],"for":[53,145],"low-power":[54],"IC":[55],"flip-flop":[59],"contains":[60],"two":[61],"secondary":[62,69,81,99],"latches.":[63],"output":[65,95],"\u201cfunction\u201d":[68],"latch":[70,82,142],"goes":[71],"following":[74],"combinational":[75,107],"circuits,":[76],"while":[77,152],"other":[79],"\u201cshadow\u201d":[80],"used":[84],"shift":[86],"vectors":[88],"By":[92],"gating":[93],"function":[98],"latch,":[100],"redundant":[102],"switching":[103,123],"activity":[104,124],"in":[105,148,174,188,203],"eliminated":[110],"shift,":[113],"thereby":[114,156],"reducing":[115],"significantly.":[120],"suppressed":[122],"also":[125,168],"lower":[128],"drop":[130],"across":[131],"chip,":[133],"increasing":[134],"chip":[136],"manufacturing":[137],"yield.":[138],"Furthermore,":[139],"shadow":[141,163,191],"reused":[144],"data":[146],"retention":[147,231],"sleep":[150],"mode":[151,177],"performing":[153],"gating,":[155],"alleviating":[157],"area":[159],"cost":[160],"latch.":[164,192],"BPS-DRFF":[167],"eases":[169],"hold":[171],"time":[172],"sign-off":[173],"due":[178],"elongated":[181],"clock-to-Q":[182],"contamination":[183],"delay":[184],"that":[185,214],"brought":[187],"by":[189],"design":[195],"applied":[197],"an":[199],"AES-128":[200],"crypto":[201],"core":[202],"UMC":[205],"55-nm":[206],"low":[207],"CMOS":[209],"technology.":[210],"Experiment":[211],"results":[212],"show":[213],"68.5%":[215],"saved":[218],"with":[222],"BPS-DRFF,":[225],"compared":[226],"standard":[229],"flip-flop.":[232]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-13T07:58:08.660418","created_date":"2025-10-10T00:00:00"}
