{"id":"https://openalex.org/W3179959500","doi":"https://doi.org/10.1109/tcsii.2021.3096193","title":"A 600-\u03bcm\u00b2 Ring-VCO-Based Hybrid PLL Using a 30-\u03bcW Charge-Sharing Integrator in 28-nm CMOS","display_name":"A 600-\u03bcm\u00b2 Ring-VCO-Based Hybrid PLL Using a 30-\u03bcW Charge-Sharing Integrator in 28-nm CMOS","publication_year":2021,"publication_date":"2021-07-12","ids":{"openalex":"https://openalex.org/W3179959500","doi":"https://doi.org/10.1109/tcsii.2021.3096193","mag":"3179959500"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2021.3096193","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3096193","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010440595","display_name":"Shiheng Yang","orcid":"https://orcid.org/0000-0002-4883-160X"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["CN","MO"],"is_corresponding":true,"raw_author_name":"Shiheng Yang","raw_affiliation_strings":["Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China","State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-4883-160X","affiliations":[{"raw_affiliation_string":"Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006541988","display_name":"Jun Yin","orcid":"https://orcid.org/0000-0002-4195-4551"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Jun Yin","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-4195-4551","affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108575617","display_name":"Tailong Xu","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Tailong Xu","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056166026","display_name":"Taimo Yi","orcid":null},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Taimo Yi","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100429915","display_name":"Qiang Li","orcid":"https://orcid.org/0000-0001-9503-995X"},"institutions":[{"id":"https://openalex.org/I150229711","display_name":"University of Electronic Science and Technology of China","ror":"https://ror.org/04qr3zq92","country_code":"CN","type":"education","lineage":["https://openalex.org/I150229711"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Li","raw_affiliation_strings":["Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China"],"raw_orcid":"https://orcid.org/0000-0001-9503-995X","affiliations":[{"raw_affiliation_string":"Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China","institution_ids":["https://openalex.org/I150229711"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]},{"raw_affiliation_string":"State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5010440595"],"corresponding_institution_ids":["https://openalex.org/I150229711","https://openalex.org/I204512498"],"apc_list":null,"apc_paid":null,"fwci":1.0167,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.75738505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":"68","issue":"9","first_page":"3108","last_page":"3112"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7056109309196472},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.6740301847457886},{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.6406786441802979},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6061326265335083},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.45595741271972656},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.44946131110191345},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4151581823825836},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.38883376121520996},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3824290335178375},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3690859079360962},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35990816354751587},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.35203468799591064},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.30663245916366577},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22108042240142822},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2126026749610901}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7056109309196472},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.6740301847457886},{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.6406786441802979},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6061326265335083},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.45595741271972656},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.44946131110191345},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4151581823825836},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.38883376121520996},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3824290335178375},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3690859079360962},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35990816354751587},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.35203468799591064},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.30663245916366577},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22108042240142822},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2126026749610901}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2021.3096193","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2021.3096193","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[{"id":"https://openalex.org/G2861840537","display_name":null,"funder_award_id":"62004028","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G3678921673","display_name":null,"funder_award_id":"MYRG2018-00220-AMSV","funder_id":"https://openalex.org/F4320322841","funder_display_name":"Universidade de Macau"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320322841","display_name":"Universidade de Macau","ror":"https://ror.org/01r4q9n85"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2020036954","https://openalex.org/W2036186630","https://openalex.org/W2086527086","https://openalex.org/W2097406868","https://openalex.org/W2105386586","https://openalex.org/W2163630970","https://openalex.org/W2295656041","https://openalex.org/W2519022190","https://openalex.org/W2591698638","https://openalex.org/W2781947136","https://openalex.org/W2895509314","https://openalex.org/W2898654478","https://openalex.org/W2913416661","https://openalex.org/W3006875805","https://openalex.org/W6733935531"],"related_works":["https://openalex.org/W2141726610","https://openalex.org/W2061664740","https://openalex.org/W1964543336","https://openalex.org/W2619153394","https://openalex.org/W2134439706","https://openalex.org/W2057338677","https://openalex.org/W4236967454","https://openalex.org/W4242529045","https://openalex.org/W2589125258","https://openalex.org/W2911266525"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"a":[3,40,66,95,111,134,155,161,168],"hybrid":[4,30,152],"PLL":[5,109,159],"by":[6,44,94],"leveraging":[7],"the":[8,16,29,56,61,71,75,80,107,151,158],"advantages":[9],"of":[10,33,74,114,137,164,170,187,195],"analog":[11],"and":[12,23,65,87,123,167,190],"digital":[13,51],"techniques":[14],"in":[15,50,104,181],"frequency-control":[17],"loop":[18,31],"to":[19,54,78,150],"achieve":[20],"ultra-compact":[21],"area":[22,113],"ultra-low":[24],"power":[25,86],"consumption":[26],"simultaneously.":[27],"Specifically,":[28],"consists":[32],"two":[34],"paths:":[35],"an":[36],"integral":[37],"path":[38,68],"features":[39],"charge-sharing":[41],"integrator":[42],"realized":[43],"switched":[45],"capacitors":[46],"with":[47],"high":[48],"precision":[49],"discrete":[52],"integration":[53],"improve":[55],"frequency":[57],"resolution":[58],"without":[59,83],"deteriorating":[60],"output":[62],"phase":[63,81,100],"noise,":[64],"proportional":[67],"directly":[69],"switches":[70],"bias":[72],"voltage":[73],"VCO":[76],"varactors":[77],"compensate":[79],"margin":[82],"costing":[84],"extra":[85],"area.":[88],"Both":[89],"paths":[90],"are":[91],"digitally":[92],"controlled":[93],"tiny":[96],"power-efficient":[97],"1-bit":[98],"bang-bang":[99],"detector":[101],"(BBPD).":[102],"Prototyped":[103],"28-nm":[105],"CMOS,":[106],"1.3-to-2.3-GHz":[108],"occupies":[110],"core":[112],"600":[115],"<inline-formula":[116,126,141,173],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[117,127,142,174,185,193],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[118,128,143,175],"<tex-math":[119,129,144,176],"notation=\"LaTeX\">$\\mu":[120,130,145],"\\text{m}~^{2}$":[121],"</tex-math></inline-formula>":[122,132,147,178],"dissipates":[124],"380":[125],"\\text{W}$":[131,146],"at":[133],"0.8-V":[135],"supply,":[136],"which":[138],"only":[139],"30":[140],"is":[148],"due":[149],"loop.":[153],"At":[154],"2.0-GHz":[156],"output,":[157],"exhibits":[160],"reference":[162],"spur":[163],"\u221260.5":[165],"dBc":[166],"jitter":[169],"1.71":[171],"ps":[172],"notation=\"LaTeX\">$_{rms}$":[177],",":[179],"resulting":[180],"state-of-the-art":[182],"FoM":[183,191],"<sub":[184,192],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">R</sub>":[186],"\u2212239.5":[188],"dB,":[189],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">NRA</sub>":[194],"\u2212271.7":[196],"dB.":[197]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":3}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}