{"id":"https://openalex.org/W3115650748","doi":"https://doi.org/10.1109/tcsii.2020.3047265","title":"Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs","display_name":"Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs","publication_year":2020,"publication_date":"2020-12-24","ids":{"openalex":"https://openalex.org/W3115650748","doi":"https://doi.org/10.1109/tcsii.2020.3047265","mag":"3115650748"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2020.3047265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.3047265","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007231589","display_name":"Mohammad Khaleqi Qaleh Jooq","orcid":"https://orcid.org/0000-0002-8537-3521"},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":true,"raw_author_name":"Mohammad Khaleqi Qaleh Jooq","raw_affiliation_strings":["Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0002-8537-3521","affiliations":[{"raw_affiliation_string":"Nanotechnology and Quantum Computing Lab, Shahid Beheshti University, Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002663856","display_name":"Mohammad Hossein Moaiyeri","orcid":"https://orcid.org/0000-0001-9711-7923"},"institutions":[{"id":"https://openalex.org/I48379061","display_name":"Shahid Beheshti University","ror":"https://ror.org/0091vmj44","country_code":"IR","type":"education","lineage":["https://openalex.org/I48379061"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Mohammad Hossein Moaiyeri","raw_affiliation_strings":["Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran"],"raw_orcid":"https://orcid.org/0000-0001-9711-7923","affiliations":[{"raw_affiliation_string":"Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran","institution_ids":["https://openalex.org/I48379061"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5031192944","display_name":"Khalil Tamersit","orcid":"https://orcid.org/0000-0002-1023-843X"},"institutions":[{"id":"https://openalex.org/I4210097536","display_name":"University of Guelma","ror":"https://ror.org/00xe6p546","country_code":"DZ","type":"education","lineage":["https://openalex.org/I4210097536"]}],"countries":["DZ"],"is_corresponding":false,"raw_author_name":"Khalil Tamersit","raw_affiliation_strings":["Department of Electronics and Telecommunications, Universit\u00e9 8 Mai 1945 Guelma, Algeria","Laboratory of Inverse Problems, Modeling, Information and Systems (PIMIS), Universit\u00e9 8 Mai 1945, Guelma, Algeria"],"raw_orcid":"https://orcid.org/0000-0002-1023-843X","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Universit\u00e9 8 Mai 1945 Guelma, Algeria","institution_ids":["https://openalex.org/I4210097536"]},{"raw_affiliation_string":"Laboratory of Inverse Problems, Modeling, Information and Systems (PIMIS), Universit\u00e9 8 Mai 1945, Guelma, Algeria","institution_ids":["https://openalex.org/I4210097536"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5007231589"],"corresponding_institution_ids":["https://openalex.org/I48379061"],"apc_list":null,"apc_paid":null,"fwci":4.2653,"has_fulltext":false,"cited_by_count":69,"citation_normalized_percentile":{"value":0.95051631,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":"68","issue":"6","first_page":"2162","last_page":"2166"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/carbon-nanotube-field-effect-transistor","display_name":"Carbon nanotube field-effect transistor","score":0.8227071762084961},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.7502765655517578},{"id":"https://openalex.org/keywords/ternary-operation","display_name":"Ternary operation","score":0.7477438449859619},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6116663217544556},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5763261318206787},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5114015936851501},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.49622565507888794},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.457235187292099},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41727519035339355},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4007495939731598},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3836013972759247},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3698723614215851},{"id":"https://openalex.org/keywords/field-effect-transistor","display_name":"Field-effect transistor","score":0.3567514717578888},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34949979186058044},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.2729187309741974},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1868745982646942},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17937242984771729},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.0984308123588562}],"concepts":[{"id":"https://openalex.org/C58916441","wikidata":"https://www.wikidata.org/wiki/Q1778563","display_name":"Carbon nanotube field-effect transistor","level":5,"score":0.8227071762084961},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.7502765655517578},{"id":"https://openalex.org/C64452783","wikidata":"https://www.wikidata.org/wiki/Q1524945","display_name":"Ternary operation","level":2,"score":0.7477438449859619},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6116663217544556},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5763261318206787},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5114015936851501},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.49622565507888794},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.457235187292099},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41727519035339355},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4007495939731598},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3836013972759247},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3698723614215851},{"id":"https://openalex.org/C145598152","wikidata":"https://www.wikidata.org/wiki/Q176097","display_name":"Field-effect transistor","level":4,"score":0.3567514717578888},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34949979186058044},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2729187309741974},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1868745982646942},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17937242984771729},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0984308123588562},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2020.3047265","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.3047265","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4399999976158142,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W2025152094","https://openalex.org/W2068871056","https://openalex.org/W2337712486","https://openalex.org/W2342750693","https://openalex.org/W2592371101","https://openalex.org/W2730326864","https://openalex.org/W2775382360","https://openalex.org/W2790390406","https://openalex.org/W2793961500","https://openalex.org/W2890687022","https://openalex.org/W2892868997","https://openalex.org/W2947141094","https://openalex.org/W2958071401","https://openalex.org/W2970187632","https://openalex.org/W2999719674","https://openalex.org/W3022068489","https://openalex.org/W3033545840","https://openalex.org/W3108766514"],"related_works":["https://openalex.org/W1017999001","https://openalex.org/W188762367","https://openalex.org/W2789662562","https://openalex.org/W4361799621","https://openalex.org/W4295177619","https://openalex.org/W2109857948","https://openalex.org/W2122777464","https://openalex.org/W2791832526","https://openalex.org/W2033476377","https://openalex.org/W2029162371"],"abstract_inverted_index":{"Ternary":[0],"logic":[1,34,73],"has":[2],"been":[3],"studied":[4],"for":[5,189],"several":[6],"decades":[7],"as":[8,169],"it":[9],"can":[10,36],"offer":[11],"significant":[12],"advantages":[13,39],"to":[14,103,140,171],"reduce":[15],"the":[16,21,26,31,47,53,57,62,97,104,114,120,126,157,172,181,186],"number":[17],"of":[18,23,30,52,61,119,128],"interconnects":[19],"and":[20,56,91,99,116,136,145,153,159,162],"complexity":[22],"operations.":[24],"However,":[25],"excessive":[27],"transistor":[28,66,100,149],"count":[29],"existing":[32],"ternary":[33,72,85,89,94,122,133,175,183],"gates":[35,138,184],"diminish":[37],"these":[38],"in":[40,125,148,156,165],"practice.":[41],"In":[42],"this":[43],"brief,":[44],"based":[45],"on":[46,141],"negative":[48],"capacitance":[49],"(NC)":[50],"feature":[51],"ferroelectric":[54],"materials":[55],"well-proven":[58],"electronic":[59],"properties":[60],"carbon":[63],"nanotube":[64],"field-effect":[65],"(CNTFET),":[67],"we":[68,80],"have":[69,81],"proposed":[70,121,132,182],"ultra-compact":[71],"gates.":[74,176],"After":[75],"developing":[76],"a":[77,83,87,92],"NC-CNTFET":[78],"model,":[79],"designed":[82],"2-transistor":[84],"inverter,":[86,134],"4-transistor":[88,93],"NAND,":[90,135],"NOR":[95,137],"with":[96],"structures":[98],"counts":[101],"similar":[102],"binary":[105],"complementary":[106],"metal-oxide-semiconductor":[107],"(CMOS)":[108],"logic.":[109],"The":[110],"simulation":[111],"results":[112],"ascertain":[113],"correct":[115],"robust":[117],"functionality":[118],"gates,":[123],"even":[124],"presence":[127],"process":[129],"variations.":[130],"Our":[131,177],"lead":[139],"average":[142],"65%,":[143],"60%,":[144],"60%":[146],"improvements":[147,155,164],"count,":[150],"79%,":[151],"83%,":[152],"77%":[154],"area,":[158],"34%,":[160],"61%,":[161],"54%":[163],"energy-delay":[166],"product":[167],"(EDP)":[168],"compared":[170],"previous":[173],"state-of-the-art":[174],"approach":[178],"accentuates":[179],"that":[180],"are":[185],"potential":[187],"candidates":[188],"demonstrating":[190],"more":[191],"complex":[192],"multi-valued":[193],"arithmetic-logic":[194],"units.":[195]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":13},{"year":2024,"cited_by_count":13},{"year":2023,"cited_by_count":7},{"year":2022,"cited_by_count":14},{"year":2021,"cited_by_count":20}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}