{"id":"https://openalex.org/W3042176402","doi":"https://doi.org/10.1109/tcsii.2020.3008069","title":"Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model","display_name":"Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model","publication_year":2020,"publication_date":"2020-07-08","ids":{"openalex":"https://openalex.org/W3042176402","doi":"https://doi.org/10.1109/tcsii.2020.3008069","mag":"3042176402"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2020.3008069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.3008069","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031376924","display_name":"Eugene Koskin","orcid":"https://orcid.org/0000-0002-4253-0312"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Eugene Koskin","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland"],"raw_orcid":"https://orcid.org/0000-0002-4253-0312","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074395223","display_name":"Pierre Bisiaux","orcid":"https://orcid.org/0000-0001-7111-4337"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Pierre Bisiaux","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland"],"raw_orcid":"https://orcid.org/0000-0001-7111-4337","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032777255","display_name":"Dimitri Galayko","orcid":"https://orcid.org/0000-0002-7056-7489"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Dimitri Galayko","raw_affiliation_strings":["LIP6, Sorbonne Universit\u00e9, Paris, France"],"raw_orcid":"https://orcid.org/0000-0002-7056-7489","affiliations":[{"raw_affiliation_string":"LIP6, Sorbonne Universit\u00e9, Paris, France","institution_ids":["https://openalex.org/I4210159731","https://openalex.org/I39804081"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001003834","display_name":"Elena Blokhina","orcid":"https://orcid.org/0000-0002-4164-4350"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]}],"countries":["IE"],"is_corresponding":false,"raw_author_name":"Elena Blokhina","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland"],"raw_orcid":"https://orcid.org/0000-0002-4164-4350","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin, Ireland","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1041,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.42360781,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"68","issue":"1","first_page":"77","last_page":"81"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9613258838653564},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6132528185844421},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.5781983733177185},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5351907014846802},{"id":"https://openalex.org/keywords/function","display_name":"Function (biology)","score":0.45947402715682983},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.4297221899032593},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.41629695892333984},{"id":"https://openalex.org/keywords/control","display_name":"Control (management)","score":0.28179359436035156},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21997910737991333},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.13664504885673523},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1254430115222931},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.07977303862571716},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07581868767738342}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9613258838653564},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6132528185844421},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.5781983733177185},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5351907014846802},{"id":"https://openalex.org/C14036430","wikidata":"https://www.wikidata.org/wiki/Q3736076","display_name":"Function (biology)","level":2,"score":0.45947402715682983},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.4297221899032593},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.41629695892333984},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.28179359436035156},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21997910737991333},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.13664504885673523},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1254430115222931},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.07977303862571716},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07581868767738342},{"id":"https://openalex.org/C78458016","wikidata":"https://www.wikidata.org/wiki/Q840400","display_name":"Evolutionary biology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsii.2020.3008069","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.3008069","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:HAL:hal-04030258v1","is_oa":false,"landing_page_url":"https://hal.science/hal-04030258","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68 (1), pp.77-81. &#x27E8;10.1109/TCSII.2020.3008069&#x27E9;","raw_type":"Journal articles"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G296308891","display_name":null,"funder_award_id":"CF-2018-0872-P","funder_id":"https://openalex.org/F4320320834","funder_display_name":"Enterprise Ireland"}],"funders":[{"id":"https://openalex.org/F4320320834","display_name":"Enterprise Ireland","ror":"https://ror.org/023z51242"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W1040801819","https://openalex.org/W1544882865","https://openalex.org/W1599994156","https://openalex.org/W1996013689","https://openalex.org/W2057845030","https://openalex.org/W2089328455","https://openalex.org/W2093481794","https://openalex.org/W2101241604","https://openalex.org/W2144581882","https://openalex.org/W2154332266","https://openalex.org/W2162645687","https://openalex.org/W2162680749","https://openalex.org/W2292796322","https://openalex.org/W2490165320","https://openalex.org/W2547192377","https://openalex.org/W2620623985","https://openalex.org/W2753327552","https://openalex.org/W2767001006","https://openalex.org/W2792873024","https://openalex.org/W2793340579","https://openalex.org/W2908478041","https://openalex.org/W2946252709","https://openalex.org/W2996914186","https://openalex.org/W3001576521","https://openalex.org/W6728941046"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2155789024","https://openalex.org/W2315668284","https://openalex.org/W3213608175","https://openalex.org/W2109491806","https://openalex.org/W3117675750","https://openalex.org/W2141743053","https://openalex.org/W2037276323","https://openalex.org/W3095633856","https://openalex.org/W2058044441"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"we":[3],"study":[4],"jitter":[5,62],"behavior":[6],"in":[7],"an":[8,13],"event-driven":[9],"self-sampled":[10],"model":[11],"of":[12,24,35,39],"All-Digital":[14],"Phase-Locked":[15],"Loop.":[16],"We":[17,28],"provide":[18],"its":[19],"steady-state":[20],"analysis":[21],"using":[22],"simulations":[23],"a":[25,33,46,52],"discrete-time":[26],"model.":[27],"show":[29],"that":[30],"digital":[31],"jitter,":[32],"function":[34],"two":[36],"control":[37,68],"parameters":[38],"the":[40,67,82],"model,":[41],"can":[42,57],"be":[43,58],"mapped":[44],"onto":[45],"on-dimensional":[47],"manifold":[48],"and":[49,77],"approximated":[50],"via":[51],"simple":[53],"function.":[54],"The":[55,70],"latter":[56],"used":[59],"to":[60],"perform":[61],"optimisation":[63],"under":[64],"constraints":[65],"for":[66],"parameters.":[69],"verification":[71],"is":[72],"done":[73],"through":[74],"FPGA":[75],"measurements":[76],"shows":[78],"excellent":[79],"agreement":[80],"with":[81],"analytic":[83],"approximation.":[84]},"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
