{"id":"https://openalex.org/W3023534315","doi":"https://doi.org/10.1109/tcsii.2020.2993447","title":"Logic Obfuscation Through Enhanced Threshold Voltage Defined Logic Family","display_name":"Logic Obfuscation Through Enhanced Threshold Voltage Defined Logic Family","publication_year":2020,"publication_date":"2020-05-08","ids":{"openalex":"https://openalex.org/W3023534315","doi":"https://doi.org/10.1109/tcsii.2020.2993447","mag":"3023534315"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2020.2993447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.2993447","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066370358","display_name":"Beomsoo Park","orcid":"https://orcid.org/0000-0002-1842-0324"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Beomsoo Park","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0002-1842-0324","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5071432833","display_name":"Nima Maghari","orcid":"https://orcid.org/0000-0002-9168-5142"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nima Maghari","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA"],"raw_orcid":"https://orcid.org/0000-0002-9168-5142","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":1.1261,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.76689729,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"67","issue":"12","first_page":"3407","last_page":"3411"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6414440870285034},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5727307200431824},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.544424831867218},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.530575692653656},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.5230967998504639},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49206632375717163},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.486433744430542},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4312950372695923},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.4160689413547516},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3429960608482361},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3253024220466614},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.2959165573120117},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29082489013671875},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23624134063720703},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21531304717063904},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2134309709072113}],"concepts":[{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6414440870285034},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5727307200431824},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.544424831867218},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.530575692653656},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.5230967998504639},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49206632375717163},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.486433744430542},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4312950372695923},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.4160689413547516},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3429960608482361},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3253024220466614},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.2959165573120117},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29082489013671875},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23624134063720703},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21531304717063904},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2134309709072113}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2020.2993447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.2993447","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1127992671","display_name":"Combating Counterfeit Analog and Mixed Signal ICs with Lightweight Embedded Mechanisms and Innovative Electrical Tests","funder_award_id":"1610075","funder_id":"https://openalex.org/F4320306076","funder_display_name":"National Science Foundation"}],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1505879652","https://openalex.org/W1602420333","https://openalex.org/W1998182128","https://openalex.org/W2052353102","https://openalex.org/W2067276029","https://openalex.org/W2161998562","https://openalex.org/W2166778460","https://openalex.org/W2192010544","https://openalex.org/W2202385382","https://openalex.org/W2426572037","https://openalex.org/W2481878620","https://openalex.org/W2791228548","https://openalex.org/W2963360895","https://openalex.org/W6635937959","https://openalex.org/W6684544287","https://openalex.org/W6687672639"],"related_works":["https://openalex.org/W2534190481","https://openalex.org/W2082591327","https://openalex.org/W2171918386","https://openalex.org/W2142702094","https://openalex.org/W2991771859","https://openalex.org/W2118487491","https://openalex.org/W2155174752","https://openalex.org/W2158157809","https://openalex.org/W321873635","https://openalex.org/W1601832081"],"abstract_inverted_index":{"Reverse":[0],"engineering":[1],"reveals":[2],"the":[3,9,22,40,59,62,79,91,97,108,118,124,135],"physical":[4],"structure":[5],"as":[6,8,32],"well":[7],"functionality":[10,81],"of":[11,54,61,94],"an":[12],"intellectual":[13],"property":[14],"(IP)":[15],"and":[16,28,96,123,151],"integrated":[17],"circuit":[18],"(IC).":[19],"This":[20],"opens":[21],"door":[23],"for":[24,51,140],"IP/IC":[25],"piracy,":[26],"counterfeiting,":[27],"malicious":[29],"attacks":[30],"such":[31],"Trojan":[33],"insertions.":[34],"Camouflaged":[35],"logic":[36,70,89,121,127,138,143],"gates":[37],"that":[38,77,134],"have":[39],"same":[41],"schematic":[42],"architecture":[43],"with":[44],"identical":[45],"layout":[46,130],"is":[47,72,104,114,145],"used":[48,115],"to":[49,57,86,102,106,116,157],"operate":[50],"different":[52],"types":[53],"Boolean":[55],"functions":[56],"prevent":[58],"de-layering":[60],"chip.":[63],"An":[64],"enhanced":[65],"threshold":[66],"voltage":[67],"(E-TVD)":[68],"defined":[69],"family":[71,122,139],"proposed":[73,125,136],"in":[74],"this":[75],"brief":[76],"prevents":[78],"internal":[80],"from":[82,100],"being":[83],"revealed.":[84],"Compared":[85],"previous":[87],"TVD":[88,120,159],"family,":[90],"total":[92],"number":[93],"transistors":[95,99],"cascaded":[98],"supply":[101],"ground":[103],"reduced":[105],"enhance":[107],"overall":[109],"performance.":[110],"A":[111],"65nm":[112],"process":[113],"compare":[117],"conventional":[119,158],"E-TVD":[126,137],"family.":[128],"Post":[129],"simulation":[131],"results":[132],"show":[133],"a":[141],"3-input":[142],"gate":[144],"34%":[146],"area":[147],"efficient,":[148],"45%":[149],"faster,":[150],"consumes":[152],"40%":[153],"less":[154],"power":[155],"compared":[156],"design.":[160]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":5}],"updated_date":"2026-08-06T08:24:18.245995","created_date":"2025-10-10T00:00:00"}
