{"id":"https://openalex.org/W3021851551","doi":"https://doi.org/10.1109/tcsii.2020.2992514","title":"Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution","display_name":"Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution","publication_year":2020,"publication_date":"2020-05-05","ids":{"openalex":"https://openalex.org/W3021851551","doi":"https://doi.org/10.1109/tcsii.2020.2992514","mag":"3021851551"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2020.2992514","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.2992514","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035645299","display_name":"Suresh Mopuri","orcid":"https://orcid.org/0000-0002-4938-4995"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Suresh Mopuri","raw_affiliation_strings":["Indian Institute of Technology Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044085104","display_name":"Amit Acharyya","orcid":"https://orcid.org/0000-0002-5636-0676"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Acharyya","raw_affiliation_strings":["Indian Institute of Technology Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Technology Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035645299"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":0.1521,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.41075269,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"67","issue":"12","first_page":"3532","last_page":"3536"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.815210223197937},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7793838381767273},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7155618071556091},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7093340158462524},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6798864603042603},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6040951609611511},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5220643877983093},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.464816153049469},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.4271325469017029},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3986421227455139},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.37285012006759644},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.35584771633148193},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.34904223680496216},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3393068313598633},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32614797353744507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11042359471321106}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.815210223197937},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7793838381767273},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7155618071556091},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7093340158462524},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6798864603042603},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6040951609611511},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5220643877983093},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.464816153049469},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.4271325469017029},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3986421227455139},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.37285012006759644},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.35584771633148193},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.34904223680496216},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3393068313598633},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32614797353744507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11042359471321106},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsii.2020.2992514","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2020.2992514","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:raiith.iith.ac.in:7972","is_oa":false,"landing_page_url":"http://raiith.iith.ac.in/7972/","pdf_url":null,"source":{"id":"https://openalex.org/S4306400292","display_name":"Research Archive of Indian Institute of Technology Hyderabad (Indian Institute of Technology Hyderabad)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I65181880","host_organization_name":"Indian Institute of Technology Hyderabad","host_organization_lineage":["https://openalex.org/I65181880"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[{"id":"https://openalex.org/G2926208065","display_name":null,"funder_award_id":"IITH/EE/F091/S8","funder_id":"https://openalex.org/F4320314786","funder_display_name":"Xilinx"}],"funders":[{"id":"https://openalex.org/F4320314786","display_name":"Xilinx","ror":"https://ror.org/01rb7bk56"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":34,"referenced_works":["https://openalex.org/W1528796998","https://openalex.org/W1861537833","https://openalex.org/W1963586531","https://openalex.org/W1970870163","https://openalex.org/W1984558333","https://openalex.org/W2022415274","https://openalex.org/W2034198879","https://openalex.org/W2037500757","https://openalex.org/W2038971587","https://openalex.org/W2049588903","https://openalex.org/W2051298848","https://openalex.org/W2054878302","https://openalex.org/W2080094161","https://openalex.org/W2106610208","https://openalex.org/W2115511410","https://openalex.org/W2115737494","https://openalex.org/W2126226587","https://openalex.org/W2133033960","https://openalex.org/W2135538875","https://openalex.org/W2141427150","https://openalex.org/W2160198056","https://openalex.org/W2166416506","https://openalex.org/W2166799841","https://openalex.org/W2174890947","https://openalex.org/W2211599813","https://openalex.org/W2289055681","https://openalex.org/W2292087755","https://openalex.org/W2293243799","https://openalex.org/W2333960593","https://openalex.org/W2777113731","https://openalex.org/W2803891793","https://openalex.org/W2892430752","https://openalex.org/W2969915553","https://openalex.org/W3151807103"],"related_works":["https://openalex.org/W4327521644","https://openalex.org/W4283025278","https://openalex.org/W2978884468","https://openalex.org/W2168413811","https://openalex.org/W2005846134","https://openalex.org/W2082432309","https://openalex.org/W817174743","https://openalex.org/W2369237035","https://openalex.org/W2948041274","https://openalex.org/W4254559750"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"we":[3],"propose":[4],"a":[5],"low":[6],"complexity":[7],"VLSI":[8,104],"architecture":[9],"design":[10],"Methodology":[11],"for":[12,51,56],"Wigner":[13],"Ville":[14],"Distribution":[15],"(WVD)":[16],"computation.":[17],"The":[18,48,75],"proposed":[19,52,76,98],"methodology":[20,53,77,99],"performs":[21],"both":[22],"auto":[23],"and":[24,61,107],"cross":[25],"WVD":[26],"computations":[27,38],"using":[28],"only":[29],"the":[30,42,45,70,85,88,97,103],"half":[31],"number":[32],"of":[33,44,87,102],"Fast":[34],"Fourier":[35],"transform":[36],"(FFT)":[37],"as":[39],"opposed":[40],"to":[41],"state":[43,86],"art":[46,89],"methodologies.":[47],"FPGA":[49,73],"implementation":[50,105],"was":[54],"performed":[55],"16":[57],"bit":[58,63],"fixed":[59],"point":[60,67],"32":[62],"single":[64],"precision":[65],"floating":[66],"numbers":[68],"on":[69],"Xilinx":[71],"Virtex-7":[72],"(XC7vx485tffg).":[74],"saves":[78],"49%":[79],"energy":[80],"consumption":[81],"when":[82],"compared":[83],"with":[84],"methodology.":[90],"However":[91],"it":[92],"can":[93],"be":[94],"noted":[95],"that":[96],"is":[100],"independent":[101],"platform":[106],"technology":[108],"node.":[109]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}