{"id":"https://openalex.org/W2898915279","doi":"https://doi.org/10.1109/tcsii.2018.2878599","title":"Coordinate Rotation-Based Design Methodology for Square Root and Division Computation","display_name":"Coordinate Rotation-Based Design Methodology for Square Root and Division Computation","publication_year":2018,"publication_date":"2018-10-30","ids":{"openalex":"https://openalex.org/W2898915279","doi":"https://doi.org/10.1109/tcsii.2018.2878599","mag":"2898915279"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2018.2878599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2878599","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035645299","display_name":"Suresh Mopuri","orcid":"https://orcid.org/0000-0002-4938-4995"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Suresh Mopuri","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087944991","display_name":"Swati Bhardwaj","orcid":"https://orcid.org/0000-0001-9534-8808"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Swati Bhardwaj","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044085104","display_name":"Amit Acharyya","orcid":"https://orcid.org/0000-0002-5636-0676"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Amit Acharyya","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Hyderabad, Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5035645299"],"corresponding_institution_ids":["https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":1.4135,"has_fulltext":false,"cited_by_count":21,"citation_normalized_percentile":{"value":0.84070022,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"66","issue":"7","first_page":"1227","last_page":"1231"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9934999942779541,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.85692298412323},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7091526985168457},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6574267148971558},{"id":"https://openalex.org/keywords/division","display_name":"Division (mathematics)","score":0.6484254598617554},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6442443132400513},{"id":"https://openalex.org/keywords/square-root","display_name":"Square root","score":0.6399696469306946},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5815226435661316},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5727437734603882},{"id":"https://openalex.org/keywords/rotation","display_name":"Rotation (mathematics)","score":0.5568667650222778},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4517303705215454},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4268478751182556},{"id":"https://openalex.org/keywords/computational-complexity-theory","display_name":"Computational complexity theory","score":0.4110538363456726},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4009694755077362},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.4006000757217407},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3843424320220947},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35890913009643555},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35269761085510254},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3494367003440857},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2611972987651825},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.24467605352401733},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20175516605377197},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10521078109741211},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07120329141616821}],"concepts":[{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.85692298412323},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7091526985168457},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6574267148971558},{"id":"https://openalex.org/C60798267","wikidata":"https://www.wikidata.org/wiki/Q1226939","display_name":"Division (mathematics)","level":2,"score":0.6484254598617554},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6442443132400513},{"id":"https://openalex.org/C11577676","wikidata":"https://www.wikidata.org/wiki/Q134237","display_name":"Square root","level":2,"score":0.6399696469306946},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5815226435661316},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5727437734603882},{"id":"https://openalex.org/C74050887","wikidata":"https://www.wikidata.org/wiki/Q848368","display_name":"Rotation (mathematics)","level":2,"score":0.5568667650222778},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4517303705215454},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4268478751182556},{"id":"https://openalex.org/C179799912","wikidata":"https://www.wikidata.org/wiki/Q205084","display_name":"Computational complexity theory","level":2,"score":0.4110538363456726},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4009694755077362},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.4006000757217407},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3843424320220947},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35890913009643555},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35269761085510254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3494367003440857},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2611972987651825},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.24467605352401733},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20175516605377197},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10521078109741211},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07120329141616821},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2018.2878599","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2878599","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W1587654378","https://openalex.org/W2011076935","https://openalex.org/W2022431531","https://openalex.org/W2025767576","https://openalex.org/W2059488875","https://openalex.org/W2112313836","https://openalex.org/W2119178646","https://openalex.org/W2127445707","https://openalex.org/W2129092784","https://openalex.org/W2133427951","https://openalex.org/W2133586141","https://openalex.org/W2133617231","https://openalex.org/W2139535992","https://openalex.org/W2140237823","https://openalex.org/W2141957537","https://openalex.org/W2150633168","https://openalex.org/W2152297169","https://openalex.org/W2160751836","https://openalex.org/W2164986356","https://openalex.org/W2293243799","https://openalex.org/W2318876804","https://openalex.org/W2329007329","https://openalex.org/W2333960593","https://openalex.org/W2545833047","https://openalex.org/W2561259954","https://openalex.org/W2750796506","https://openalex.org/W4254421562","https://openalex.org/W6656918489","https://openalex.org/W6684140934","https://openalex.org/W6684301724"],"related_works":["https://openalex.org/W2375598816","https://openalex.org/W2379157082","https://openalex.org/W907492214","https://openalex.org/W2401971123","https://openalex.org/W2350220561","https://openalex.org/W2123696527","https://openalex.org/W2539913202","https://openalex.org/W1976822747","https://openalex.org/W2135852662","https://openalex.org/W2783110569"],"abstract_inverted_index":{"In":[0],"this":[1],"brief,":[2],"we":[3],"propose":[4],"a":[5,35],"low-complexity":[6],"design":[7],"methodology":[8,30,91],"to":[9],"compute":[10],"square-root":[11],"and":[12,41,54,77,99],"division":[13,42],"using":[14,66],"circular":[15],"coordinate":[16],"rotation":[17],"digital":[18],"computer":[19],"(CORDIC).":[20],"Unlike":[21],"the":[22,25,28,32,45,50,60,89,96],"state":[23],"of":[24,34,59,88],"art":[26],"methods,":[27],"proposed":[29,61,90],"eliminates":[31],"requirement":[33],"separate":[36],"hardware":[37],"for":[38],"square":[39],"root":[40],"computation":[43],"in":[44],"CORDIC-based":[46],"applications":[47],"without":[48,106],"compromising":[49],"computational":[51],"speed,":[52],"throughput":[53],"accuracy.":[55],"The":[56,86],"ASIC":[57],"implementation":[58],"architecture":[62],"has":[63,83,92],"been":[64,84,93],"performed":[65],"UMC":[67],"90":[68],"nm":[69],"Technology":[70],"node":[71],"with":[72,95],"1.08":[73],"V":[74],"@1":[75],"MHz":[76],"subsequently":[78],"Xilinx":[79],"Virtex-6":[80],"(XC6v1x240t)-based":[81],"FPGA-prototyping":[82],"done.":[85],"performance":[87],"compared":[94],"reported":[97],"literature":[98],"significant":[100],"power":[101],"consumption":[102],"improvement":[103],"was":[104],"observed":[105],"any":[107],"additional":[108],"area":[109],"overhead.":[110]},"counts_by_year":[{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}