{"id":"https://openalex.org/W2888740128","doi":"https://doi.org/10.1109/tcsii.2018.2866231","title":"Libra: An Automatic Design Methodology for CMOS Complex Gates","display_name":"Libra: An Automatic Design Methodology for CMOS Complex Gates","publication_year":2018,"publication_date":"2018-08-20","ids":{"openalex":"https://openalex.org/W2888740128","doi":"https://doi.org/10.1109/tcsii.2018.2866231","mag":"2888740128"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2018.2866231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2866231","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070246186","display_name":"Maicon S. Cardoso","orcid":"https://orcid.org/0000-0002-8967-7864"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Maicon S. Cardoso","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041919625","display_name":"Gustavo H. Smaniotto","orcid":"https://orcid.org/0000-0002-0862-3910"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Gustavo H. Smaniotto","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063386369","display_name":"Andrei A. O. Bubolz","orcid":"https://orcid.org/0000-0002-0116-9946"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Andrei A. O. Bubolz","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101963901","display_name":"Matheus T. Moreira","orcid":"https://orcid.org/0000-0001-5030-9215"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Matheus T. Moreira","raw_affiliation_strings":["Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Pontifical Catholic University of Rio Grande do Sul, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar S. da Rosa","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068796829","display_name":"Felipe Marques","orcid":"https://orcid.org/0000-0003-1318-9992"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe de S. Marques","raw_affiliation_strings":["Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5070246186"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.515,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.6752009,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"65","issue":"10","first_page":"1345","last_page":"1349"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.991100013256073,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7248965501785278},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.542864203453064},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4026423692703247},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36875414848327637},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3463210463523865},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26511073112487793}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7248965501785278},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.542864203453064},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4026423692703247},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36875414848327637},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3463210463523865},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26511073112487793}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2018.2866231","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2866231","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W574738980","https://openalex.org/W2014840902","https://openalex.org/W2015987974","https://openalex.org/W2018989845","https://openalex.org/W2027484829","https://openalex.org/W2031298013","https://openalex.org/W2040537281","https://openalex.org/W2088115909","https://openalex.org/W2116118782","https://openalex.org/W2121655825","https://openalex.org/W2144613608","https://openalex.org/W2183797205","https://openalex.org/W2758158941","https://openalex.org/W6654308295","https://openalex.org/W6657344253","https://openalex.org/W6744419797"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W4386230336","https://openalex.org/W2109445684"],"abstract_inverted_index":{"Recent":[0],"papers":[1],"have":[2,169],"shown":[3,170],"that":[4,171],"the":[5,21,48,54,62,70,80,88,95,160,185,189],"circuit":[6,55,81],"design":[7,96],"based":[8,104],"on":[9,79,105],"complex":[10,99,165],"gates":[11],"generated":[12],"under":[13,131],"demand":[14],"became":[15],"a":[16,35,106,121,127],"valuable":[17],"alternative":[18],"to":[19,46,112,155,184],"surpass":[20],"well-known":[22],"standard":[23],"cell":[24],"approach,":[25],"especially":[26],"for":[27,94,164],"critical":[28],"parts":[29],"of":[30,50,73,97,179],"digital":[31,74],"systems,":[32],"which":[33,133],"contains":[34],"high":[36],"restrictive":[37],"specification":[38],"level.":[39],"Through":[40],"this":[41,65,84],"strategy,":[42],"it":[43,119,142,152],"is":[44,67,103,153],"possible":[45,154],"minimize":[47],"number":[49],"transistors,":[51],"potentially":[52],"optimizing":[53],"in":[56,177],"electrical":[57],"and":[58,76,126,138,147,181],"geometrical":[59],"domains.":[60],"On":[61],"other":[63],"hand,":[64],"paradigm":[66,110],"limited":[68],"considering":[69],"increasing":[71],"complexity":[72],"systems":[75],"its":[77],"dependence":[78],"designer.":[82],"In":[83],"scenario,":[85],"we":[86],"propose":[87],"Libra":[89,102,172],"methodology,":[90],"an":[91],"automatic":[92,135],"approach":[93],"CMOS":[98],"logic":[100],"gates.":[101],"transistor":[107],"network":[108],"generation":[109,129],"capable":[111],"deliver":[113,174],"solutions":[114,186],"with":[115,159],"diversified":[116],"topologies.":[117],"Furthermore,":[118],"has":[120],"flexible":[122],"gate":[123,166],"sizing":[124],"methodology":[125],"layout":[128],"process":[130],"demand,":[132],"includes":[134],"placement,":[136],"routing,":[137],"compaction.":[139],"Besides":[140],"that,":[141],"implements":[143],"on-the-fly":[144],"validation,":[145],"verification":[146],"test":[148],"routines.":[149],"This":[150],"way,":[151],"compare":[156],"our":[157],"tool":[158],"widely":[161],"used":[162],"method":[163],"design.":[167],"Experiments":[168],"can":[173],"optimized":[175],"cells":[176],"terms":[178],"area":[180],"delay":[182],"relative":[183],"obtained":[187],"from":[188],"usual":[190],"Boolean":[191],"factoring":[192],"paradigm.":[193]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
