{"id":"https://openalex.org/W2797449020","doi":"https://doi.org/10.1109/tcsii.2018.2826014","title":"A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs","display_name":"A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs","publication_year":2018,"publication_date":"2018-04-12","ids":{"openalex":"https://openalex.org/W2797449020","doi":"https://doi.org/10.1109/tcsii.2018.2826014","mag":"2797449020"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2018.2826014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2826014","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://www.research.ed.ac.uk/en/publications/2b558f3f-ad42-4c89-a923-094b5b649664","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038402408","display_name":"Godwin Enemali","orcid":"https://orcid.org/0000-0003-2686-7035"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Godwin Enemali","raw_affiliation_strings":["School of Engineering, University of Edinburgh, Edinburgh, U.K"],"raw_orcid":"https://orcid.org/0000-0003-2686-7035","affiliations":[{"raw_affiliation_string":"School of Engineering, University of Edinburgh, Edinburgh, U.K","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032547513","display_name":"Adewale Adetomi","orcid":"https://orcid.org/0000-0003-0720-3313"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Adewale Adetomi","raw_affiliation_strings":["School of Engineering, University of Edinburgh, Edinburgh, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, University of Edinburgh, Edinburgh, U.K","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078405996","display_name":"G. Seetharaman","orcid":"https://orcid.org/0000-0001-7764-0661"},"institutions":[{"id":"https://openalex.org/I3131484930","display_name":"National Institute of Technology Nagaland","ror":"https://ror.org/04cbvzp68","country_code":"IN","type":"education","lineage":["https://openalex.org/I3131484930"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Gopalakrishnan Seetharaman","raw_affiliation_strings":["Department of ECE, National Institute of Technology Nagaland, Dimapur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE, National Institute of Technology Nagaland, Dimapur, India","institution_ids":["https://openalex.org/I3131484930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022272531","display_name":"Tughrul Arslan","orcid":"https://orcid.org/0000-0001-8176-5803"},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Tughrul Arslan","raw_affiliation_strings":["School of Engineering, University of Edinburgh, Edinburgh, U.K"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering, University of Edinburgh, Edinburgh, U.K","institution_ids":["https://openalex.org/I98677209"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5038402408"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.5235,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.66899686,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"65","issue":"5","first_page":"612","last_page":"616"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/relocation","display_name":"Relocation","score":0.9241389632225037},{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.8805543780326843},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8093167543411255},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7506213188171387},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5687454342842102},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5510129928588867},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.15761321783065796},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12046456336975098},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08667808771133423}],"concepts":[{"id":"https://openalex.org/C2779019381","wikidata":"https://www.wikidata.org/wiki/Q3499564","display_name":"Relocation","level":2,"score":0.9241389632225037},{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.8805543780326843},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8093167543411255},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7506213188171387},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5687454342842102},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5510129928588867},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.15761321783065796},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12046456336975098},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08667808771133423}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/tcsii.2018.2826014","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2018.2826014","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:pure.ed.ac.uk:openaire/2b558f3f-ad42-4c89-a923-094b5b649664","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/2b558f3f-ad42-4c89-a923-094b5b649664","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Arslan, T, Enemali, G I & Adetomi, A 2018, 'A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 612-616. https://doi.org/10.1109/TCSII.2018.2826014","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:researchonline.gcu.ac.uk:openaire_cris_publications/bf93b709-f100-4cfd-a28b-e91c7c1ae792","is_oa":false,"landing_page_url":"https://researchonline.gcu.ac.uk/en/publications/bf93b709-f100-4cfd-a28b-e91c7c1ae792","pdf_url":null,"source":{"id":"https://openalex.org/S4306402566","display_name":"ResearchOnline (Glasgow Caledonian University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I195939026","host_organization_name":"Glasgow Caledonian University","host_organization_lineage":["https://openalex.org/I195939026"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"Enemali , G , Adetomi , A , Seetharaman , G & Arslan , T 2018 , ' A functionality-based runtime relocation system for circuits on heterogeneous FPGAs ' , IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 65 , no. 5 , pp. 612-616 . https://doi.org/10.1109/TCSII.2018.2826014","raw_type":"article"},{"id":"pmh:oai:pure.ed.ac.uk:publications/2b558f3f-ad42-4c89-a923-094b5b649664","is_oa":false,"landing_page_url":"http://hdl.handle.net/20.500.11820/2b558f3f-ad42-4c89-a923-094b5b649664","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":{"id":"pmh:oai:pure.ed.ac.uk:openaire/2b558f3f-ad42-4c89-a923-094b5b649664","is_oa":true,"landing_page_url":"https://www.research.ed.ac.uk/en/publications/2b558f3f-ad42-4c89-a923-094b5b649664","pdf_url":null,"source":{"id":"https://openalex.org/S4406922455","display_name":"Edinburgh Research Explorer","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Arslan, T, Enemali, G I & Adetomi, A 2018, 'A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs', IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 612-616. https://doi.org/10.1109/TCSII.2018.2826014","raw_type":"info:eu-repo/semantics/publishedVersion"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1977850862","https://openalex.org/W1995232958","https://openalex.org/W2008152292","https://openalex.org/W2033730497","https://openalex.org/W2039535443","https://openalex.org/W2101906611","https://openalex.org/W2117513278","https://openalex.org/W2154002295","https://openalex.org/W2162113238","https://openalex.org/W2172029260","https://openalex.org/W2740628125","https://openalex.org/W2756854605","https://openalex.org/W2757326062","https://openalex.org/W2760744041","https://openalex.org/W2762119053"],"related_works":["https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W4323831234","https://openalex.org/W2544043553","https://openalex.org/W2121309702","https://openalex.org/W4311839959","https://openalex.org/W49599899","https://openalex.org/W3217774925","https://openalex.org/W2040087757","https://openalex.org/W2009741039"],"abstract_inverted_index":{"Runtime":[0],"relocation":[1,36,50,60,116,120,156,167],"of":[2,32,100,126,139,146,160],"circuits":[3],"on":[4,52,57,86],"field-programmable":[5],"gate":[6],"arrays":[7],"(FPGAs)":[8],"has":[9],"been":[10],"proposed":[11,128],"for":[12,81,169],"achieving":[13],"many":[14],"desirable":[15],"features":[16],"including":[17],"fault":[18],"tolerance,":[19],"defragmentation,":[20],"and":[21,47,65,92,134,165],"system":[22],"load":[23],"balancing.":[24],"However,":[25],"the":[26,29,63,71,78,124,127,144,158],"changes":[27],"in":[28,143],"architectural":[30],"composition":[31],"FPGAs":[33,41,53],"have":[34,42,54],"made":[35],"more":[37,44],"challenging":[38],"mainly":[39],"because":[40],"become":[43],"heterogeneous.":[45],"Previous":[46],"state-of-the-art":[48],"circuit":[49,110],"systems":[51],"relied":[55],"only":[56,153],"direct":[58,114,154],"bitstream":[59,80,115,155],"which":[61,112],"requires":[62],"source":[64],"destination":[66],"resource":[67],"layouts":[68],"to":[69,77,97,152],"be":[70,95,149],"same,":[72],"as":[73,75],"well":[74],"access":[76],"design":[79],"manipulation.":[82],"Hence,":[83],"their":[84],"efficiency":[85],"modern":[87],"heterogeneous":[88],"chips":[89],"greatly":[90],"reduces,":[91],"mostly":[93],"cannot":[94],"applied":[96],"encrypted":[98],"bitstreams":[99],"intellectual":[101],"property":[102],"blocks.":[103],"In":[104],"this":[105,170],"brief,":[106],"we":[107],"present":[108],"a":[109,118,131,161],"relocator":[111],"augments":[113],"with":[117],"functionality-based":[119],"scheme.":[121],"We":[122],"demonstrate":[123],"feasibility":[125],"technique":[129],"using":[130],"CORDIC":[132],"application":[133],"show":[135],"that":[136],"an":[137],"average":[138],"over":[140],"2.6-fold":[141],"increase":[142],"number":[145],"relocations":[147],"can":[148],"obtained":[150],"compared":[151],"at":[157],"expense":[159],"small":[162],"memory":[163],"overhead":[164],"manageable":[166],"time":[168],"case":[171],"study.":[172]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
