{"id":"https://openalex.org/W2655532174","doi":"https://doi.org/10.1109/tcsii.2017.2717490","title":"A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection","display_name":"A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection","publication_year":2017,"publication_date":"2017-06-20","ids":{"openalex":"https://openalex.org/W2655532174","doi":"https://doi.org/10.1109/tcsii.2017.2717490","mag":"2655532174"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2017.2717490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2017.2717490","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025171789","display_name":"Luis Alberto Aranda","orcid":"https://orcid.org/0000-0003-4458-9761"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Luis Alberto Aranda","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":"https://orcid.org/0000-0003-4458-9761","affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080322790","display_name":"Pedro Reviriego","orcid":"https://orcid.org/0000-0003-2540-5234"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Pedro Reviriego","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044495372","display_name":"Juan Antonio Maestro","orcid":"https://orcid.org/0000-0001-7133-9026"},"institutions":[{"id":"https://openalex.org/I3020445194","display_name":"Universidad Nebrija","ror":"https://ror.org/03tzyrt94","country_code":"ES","type":"education","lineage":["https://openalex.org/I3020445194"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Juan Antonio Maestro","raw_affiliation_strings":["ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARIES Research Center, Universidad Antonio de Nebrija, Madrid, Spain","institution_ids":["https://openalex.org/I3020445194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I3020445194"],"apc_list":null,"apc_paid":null,"fwci":0.5632,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.6845947,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"65","issue":"3","first_page":"376","last_page":"380"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10780","display_name":"Reliability and Maintenance Optimization","score":0.9914000034332275,"subfield":{"id":"https://openalex.org/subfields/2213","display_name":"Safety, Risk, Reliability and Quality"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9884999990463257,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.837821364402771},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.7770581245422363},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6919291019439697},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5779176354408264},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5670799016952515},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.5176339745521545},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.4958120286464691},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.4843243360519409},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48059865832328796},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.4462580978870392},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.4249570071697235},{"id":"https://openalex.org/keywords/single-event-upset","display_name":"Single event upset","score":0.42416924238204956},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3543597459793091},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3392750024795532},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2631390690803528},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1666601598262787},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.06958979368209839}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.837821364402771},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.7770581245422363},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6919291019439697},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5779176354408264},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5670799016952515},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.5176339745521545},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.4958120286464691},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.4843243360519409},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48059865832328796},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.4462580978870392},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.4249570071697235},{"id":"https://openalex.org/C2780073065","wikidata":"https://www.wikidata.org/wiki/Q1476733","display_name":"Single event upset","level":3,"score":0.42416924238204956},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3543597459793091},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3392750024795532},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2631390690803528},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1666601598262787},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.06958979368209839},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2017.2717490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2017.2717490","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7611336909","display_name":null,"funder_award_id":"ESP2014-54505-C2-1-R","funder_id":"https://openalex.org/F4320321837","funder_display_name":"Ministerio de Econom\u00eda y Competitividad"}],"funders":[{"id":"https://openalex.org/F4320321837","display_name":"Ministerio de Econom\u00eda y Competitividad","ror":"https://ror.org/034900433"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1497850294","https://openalex.org/W1587379812","https://openalex.org/W1587462691","https://openalex.org/W1766888123","https://openalex.org/W1991756600","https://openalex.org/W1996708669","https://openalex.org/W2079749239","https://openalex.org/W2080933453","https://openalex.org/W2081215702","https://openalex.org/W2099569658","https://openalex.org/W2107406097","https://openalex.org/W2125139996","https://openalex.org/W2127871209","https://openalex.org/W2153953229","https://openalex.org/W2171823768","https://openalex.org/W2328083745","https://openalex.org/W3149410719","https://openalex.org/W4302116677","https://openalex.org/W6635347194","https://openalex.org/W6755211261"],"related_works":["https://openalex.org/W3208260600","https://openalex.org/W3006277082","https://openalex.org/W3003557214","https://openalex.org/W2065552285","https://openalex.org/W3156329500","https://openalex.org/W1493283943","https://openalex.org/W4381549462","https://openalex.org/W2387824216","https://openalex.org/W19802766","https://openalex.org/W2610634993"],"abstract_inverted_index":{"Compared":[0],"with":[1,93],"application":[2],"specific":[3],"integrated":[4],"circuits":[5],"(ASICs),":[6],"static":[7],"random":[8],"access":[9],"memory":[10,25,43],"(SRAM)-based":[11],"field":[12],"programmable":[13],"gate":[14],"arrays":[15],"(FPGAs)":[16],"respond":[17],"differently":[18],"to":[19,22,41,102,137],"radiation":[20],"due":[21,40],"the":[23,30,33,49,114,142,151],"configuration":[24,42],"vulnerability.":[26],"In":[27,62],"this":[28],"brief,":[29],"differences":[31],"between":[32],"permanent":[34],"error":[35,52,59,66,143],"model":[36,53],"for":[37,58,70],"SRAM-based":[38,83,174],"FPGAs":[39],"single":[44],"event":[45],"upsets":[46],"(SEUs),":[47],"and":[48,79],"ASIC":[50],"SEU":[51],"are":[54,134],"put":[55],"into":[56],"perspective":[57],"detection":[60,67,144],"schemes.":[61],"particular,":[63],"a":[64,94,104,162],"concurrent":[65],"(CED)":[68],"technique":[69,116],"finite":[71],"impulse":[72],"response":[73],"filters":[74],"in":[75,81,100,139,159,173],"ASICs":[76],"is":[77,91,157],"implemented":[78],"evaluated":[80],"an":[82],"FPGA":[84,148],"through":[85],"fault":[86,126],"injection":[87,127],"emulation.":[88],"This":[89,154],"method":[90],"compared":[92],"dual":[95],"modular":[96],"redundancy":[97],"(DMR)":[98],"scheme":[99],"order":[101],"obtain":[103],"common":[105],"behavior.":[106],"The":[107],"analysis":[108],"of":[109],"experimental":[110],"data":[111],"indicates":[112],"that":[113,130],"CED":[115],"has":[117],"less":[118],"undetected":[119],"errors":[120],"than":[121,150],"DMR.":[122],"However,":[123],"our":[124],"exhaustive":[125],"tests":[128],"reveal":[129],"false":[131],"positive":[132],"detections":[133],"more":[135,147],"likely":[136],"occur":[138],"CED,":[140],"since":[141],"branch":[145],"uses":[146],"resources":[149],"DMR":[152],"comparator.":[153],"phenomenon,":[155],"which":[156],"negligible":[158],"ASICs,":[160],"implies":[161],"partial":[163],"or":[164],"complete":[165],"unnecessary":[166],"reconfiguration,":[167],"so":[168],"it":[169],"should":[170],"be":[171],"considered":[172],"FPGAs.":[175]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}