{"id":"https://openalex.org/W2607342090","doi":"https://doi.org/10.1109/tcsii.2017.2695162","title":"An Amplified Offset Compensation Scheme and Its Application in a Track and Hold Circuit","display_name":"An Amplified Offset Compensation Scheme and Its Application in a Track and Hold Circuit","publication_year":2017,"publication_date":"2017-04-19","ids":{"openalex":"https://openalex.org/W2607342090","doi":"https://doi.org/10.1109/tcsii.2017.2695162","mag":"2607342090"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2017.2695162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2017.2695162","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://idus.us.es/handle//11441/141615","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5032973784","display_name":"Shirin Pourashraf","orcid":"https://orcid.org/0000-0001-8013-1171"},"institutions":[{"id":"https://openalex.org/I10052268","display_name":"New Mexico State University","ror":"https://ror.org/00hpz7z43","country_code":"US","type":"education","lineage":["https://openalex.org/I10052268"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shirin Pourashraf","raw_affiliation_strings":["VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA"],"raw_orcid":"https://orcid.org/0000-0001-8013-1171","affiliations":[{"raw_affiliation_string":"VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA","institution_ids":["https://openalex.org/I10052268"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045738320","display_name":"J. Ram\u0131\u0301rez-Angulo","orcid":"https://orcid.org/0000-0001-5977-616X"},"institutions":[{"id":"https://openalex.org/I10052268","display_name":"New Mexico State University","ror":"https://ror.org/00hpz7z43","country_code":"US","type":"education","lineage":["https://openalex.org/I10052268"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jaime Ramirez-Angulo","raw_affiliation_strings":["VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA"],"raw_orcid":"https://orcid.org/0000-0001-5977-616X","affiliations":[{"raw_affiliation_string":"VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, USA","institution_ids":["https://openalex.org/I10052268"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073511098","display_name":"Alfonso R. Cabrera-Galicia","orcid":"https://orcid.org/0009-0003-5088-6487"},"institutions":[{"id":"https://openalex.org/I39824353","display_name":"National Institute of Astrophysics, Optics and Electronics","ror":"https://ror.org/00bpmmc63","country_code":"MX","type":"facility","lineage":["https://openalex.org/I39824353"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Alfonso R. Cabrera-Galicia","raw_affiliation_strings":["Electronics Department, National Institute for Astrophysics, Optics, and Electronics, Puebla, Mexico"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Department, National Institute for Astrophysics, Optics, and Electronics, Puebla, Mexico","institution_ids":["https://openalex.org/I39824353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084248588","display_name":"Antonio J. L\u00f3pez\u2010Mart\u00edn","orcid":"https://orcid.org/0000-0001-7629-0305"},"institutions":[{"id":"https://openalex.org/I175051016","display_name":"Universidad P\u00fablica de Navarra (UPNA)","ror":"https://ror.org/02z0cah89","country_code":"ES","type":"education","lineage":["https://openalex.org/I175051016"]},{"id":"https://openalex.org/I88155538","display_name":"Universidad de Navarra","ror":"https://ror.org/02rxc7m23","country_code":"ES","type":"education","lineage":["https://openalex.org/I88155538"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Antonio J. Lopez-Martin","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, Public University of Navarra, Pamplona, Spain"],"raw_orcid":"https://orcid.org/0000-0001-7629-0305","affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, Public University of Navarra, Pamplona, Spain","institution_ids":["https://openalex.org/I175051016","https://openalex.org/I88155538"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089442866","display_name":"R.G. Carvajal","orcid":"https://orcid.org/0000-0003-3891-8987"},"institutions":[{"id":"https://openalex.org/I79238269","display_name":"Universidad de Sevilla","ror":"https://ror.org/03yxnpp24","country_code":"ES","type":"education","lineage":["https://openalex.org/I79238269"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Ramon Gonz\u00e1lez-Carvajal","raw_affiliation_strings":["Departamento de Ingenier&#x00ED;a Electr&#x00F3;nica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain","Departamento de Ingenier\u00eda Electr\u00f3nica, Universidad de Sevilla, Sevilla, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Departamento de Ingenier&#x00ED;a Electr&#x00F3;nica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]},{"raw_affiliation_string":"Departamento de Ingenier\u00eda Electr\u00f3nica, Universidad de Sevilla, Sevilla, Spain","institution_ids":["https://openalex.org/I79238269"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1695,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.79859201,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"65","issue":"4","first_page":"416","last_page":"420"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.8462800979614258},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.5505738258361816},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5374755263328552},{"id":"https://openalex.org/keywords/dc-bias","display_name":"DC bias","score":0.5204877257347107},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5013918876647949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49605926871299744},{"id":"https://openalex.org/keywords/track","display_name":"Track (disk drive)","score":0.43917131423950195},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4372224509716034},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43032339215278625},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3913264274597168},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.34443873167037964},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.29826438426971436},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27509605884552},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.08400660753250122}],"concepts":[{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.8462800979614258},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.5505738258361816},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5374755263328552},{"id":"https://openalex.org/C88682704","wikidata":"https://www.wikidata.org/wiki/Q2907415","display_name":"DC bias","level":3,"score":0.5204877257347107},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5013918876647949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49605926871299744},{"id":"https://openalex.org/C89992363","wikidata":"https://www.wikidata.org/wiki/Q5961558","display_name":"Track (disk drive)","level":2,"score":0.43917131423950195},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4372224509716034},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43032339215278625},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3913264274597168},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.34443873167037964},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.29826438426971436},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27509605884552},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.08400660753250122},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsii.2017.2695162","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2017.2695162","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:idus.us.es:11441/141615","is_oa":true,"landing_page_url":"https://idus.us.es/handle//11441/141615","pdf_url":null,"source":{"id":"https://openalex.org/S4306400333","display_name":"idUS (Universidad de Sevilla)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:idus.us.es:11441/141615","is_oa":true,"landing_page_url":"https://idus.us.es/handle//11441/141615","pdf_url":null,"source":{"id":"https://openalex.org/S4306400333","display_name":"idUS (Universidad de Sevilla)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79238269","host_organization_name":"Universidad de Sevilla","host_organization_lineage":["https://openalex.org/I79238269"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by-nc-nd","license_id":"https://openalex.org/licenses/cc-by-nc-nd","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1505760695","https://openalex.org/W2105331580","https://openalex.org/W2106049701","https://openalex.org/W2125666370","https://openalex.org/W2127142182","https://openalex.org/W2130839217","https://openalex.org/W2137348752","https://openalex.org/W2159371590","https://openalex.org/W2577762902","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2789518417","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W1965493748","https://openalex.org/W2889361259","https://openalex.org/W2115447424","https://openalex.org/W2886612787","https://openalex.org/W2093726221","https://openalex.org/W2054505526"],"abstract_inverted_index":{"This":[0,42],"brief":[1],"proposes":[2],"a":[3,11,61],"fully":[4],"differential":[5],"track":[6,37],"and":[7,50],"hold":[8,27],"circuit":[9],"using":[10],"new":[12],"dc":[13],"offset":[14,24,55],"compensation":[15,56],"scheme.":[16,71],"It":[17],"stores":[18],"an":[19],"amplified":[20],"version":[21],"of":[22,60],"the":[23,26,36,69],"during":[25,35],"phase,":[28],"which":[29],"is":[30,44],"used":[31],"in":[32,64],"attenuated":[33],"fashion":[34],"phase":[38],"to":[39,47],"compensate":[40],"offset.":[41],"scheme":[43],"less":[45],"sensitive":[46],"charge":[48],"injection":[49],"other":[51],"errors":[52],"than":[53],"conventional":[54],"schemes.":[57],"Experimental":[58],"results":[59],"test":[62],"chip":[63],"0.18-\u03bcm":[65],"CMOS":[66],"technology":[67],"verify":[68],"proposed":[70]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
