{"id":"https://openalex.org/W2347156424","doi":"https://doi.org/10.1109/tcsii.2016.2563798","title":"HUB Floating Point for Improving FPGA Implementations of DSP Applications","display_name":"HUB Floating Point for Improving FPGA Implementations of DSP Applications","publication_year":2016,"publication_date":"2016-05-05","ids":{"openalex":"https://openalex.org/W2347156424","doi":"https://doi.org/10.1109/tcsii.2016.2563798","mag":"2347156424"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2016.2563798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2563798","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019066865","display_name":"Javier Hormigo","orcid":"https://orcid.org/0000-0002-5454-6821"},"institutions":[{"id":"https://openalex.org/I82767444","display_name":"Universidad de M\u00e1laga","ror":"https://ror.org/036b2ww28","country_code":"ES","type":"education","lineage":["https://openalex.org/I82767444"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Javier Hormigo","raw_affiliation_strings":["Department of Computer Architecture, Universidad de M\u00e1laga, M\u00e1laga, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Universidad de M\u00e1laga, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I82767444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089234420","display_name":"Julio Villalba","orcid":"https://orcid.org/0000-0001-8557-3876"},"institutions":[{"id":"https://openalex.org/I82767444","display_name":"Universidad de M\u00e1laga","ror":"https://ror.org/036b2ww28","country_code":"ES","type":"education","lineage":["https://openalex.org/I82767444"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Julio Villalba","raw_affiliation_strings":["Department of Computer Architecture, Universidad de M\u00e1laga, M\u00e1laga, Spain"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Architecture, Universidad de M\u00e1laga, M\u00e1laga, Spain","institution_ids":["https://openalex.org/I82767444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I82767444"],"apc_list":null,"apc_paid":null,"fwci":2.4583,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.89763972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"64","issue":"3","first_page":"319","last_page":"323"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/rounding","display_name":"Rounding","score":0.8350866436958313},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8306456804275513},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.755233645439148},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6909463405609131},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6830134987831116},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.6048852205276489},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.550270140171051},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4616682827472687},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.4445647895336151},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4304690361022949},{"id":"https://openalex.org/keywords/arithmetic-logic-unit","display_name":"Arithmetic logic unit","score":0.4255399703979492},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.42146602272987366},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.386112242937088},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3417026400566101},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1930147111415863},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13416188955307007},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09598022699356079},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.0736226737499237}],"concepts":[{"id":"https://openalex.org/C136625980","wikidata":"https://www.wikidata.org/wiki/Q663208","display_name":"Rounding","level":2,"score":0.8350866436958313},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8306456804275513},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.755233645439148},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6909463405609131},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6830134987831116},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.6048852205276489},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.550270140171051},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4616682827472687},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.4445647895336151},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4304690361022949},{"id":"https://openalex.org/C100276221","wikidata":"https://www.wikidata.org/wiki/Q192903","display_name":"Arithmetic logic unit","level":2,"score":0.4255399703979492},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.42146602272987366},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.386112242937088},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3417026400566101},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1930147111415863},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13416188955307007},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09598022699356079},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0736226737499237},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2016.2563798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2563798","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.49000000953674316,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1491307824","https://openalex.org/W1496069875","https://openalex.org/W1499466461","https://openalex.org/W1910521375","https://openalex.org/W2030898836","https://openalex.org/W2034749845","https://openalex.org/W2042727501","https://openalex.org/W2085973257","https://openalex.org/W2106942255","https://openalex.org/W2155598726","https://openalex.org/W2342490988","https://openalex.org/W2416197829"],"related_works":["https://openalex.org/W2535419677","https://openalex.org/W2118569990","https://openalex.org/W2134876043","https://openalex.org/W187939582","https://openalex.org/W3207167822","https://openalex.org/W4322008031","https://openalex.org/W2544512391","https://openalex.org/W2950918715","https://openalex.org/W1495488519","https://openalex.org/W1754225066"],"abstract_inverted_index":{"The":[0],"increasing":[1],"complexity":[2],"of":[3,14,30,55,86,104,118,130],"new":[4,47],"digital":[5],"signal":[6],"processing":[7],"(DSP)":[8],"applications":[9,40],"is":[10],"forcing":[11],"the":[12,28,52,56,87,105,108,116,145],"use":[13,113],"floating":[15],"point":[16],"(FP)":[17],"numbers":[18],"in":[19],"their":[20],"hardware":[21],"implementations.":[22,79],"In":[23,102],"this":[24],"brief,":[25],"we":[26,64],"investigate":[27],"advantages":[29],"using":[31,99],"half-unit":[32],"biased":[33],"(HUB)":[34],"formats":[35,49,71],"to":[36],"implement":[37],"these":[38,119],"FP":[39,48,60,92,120],"on":[41,59,76,96],"field-programmable":[42],"gate":[43],"arrays":[44],"(FPGAs).":[45],"These":[46],"allow":[50],"for":[51,134],"effective":[53],"elimination":[54],"rounding":[57],"logic":[58],"arithmetic":[61],"units.":[62],"First,":[63],"experimentally":[65],"show":[66],"that":[67,129],"HUB":[68,100,109,138],"and":[69,94,114],"standard":[70],"provide":[72],"equivalent":[73,126],"signal-to-noise":[74],"ratio":[75],"DSP":[77],"application":[78],"We":[80],"then":[81],"present":[82],"a":[83],"detailed":[84],"study":[85],"improvement":[88],"achieved":[89],"when":[90],"implementing":[91],"adders":[93],"multipliers":[95,139],"FPGAs":[97],"by":[98],"numbers.":[101],"most":[103],"cases":[106],"studied,":[107],"approach":[110],"reduces":[111],"resource":[112],"increases":[115],"speed":[117],"units":[121],"while":[122],"always":[123],"providing":[124],"statistically":[125],"accuracy":[127],"as":[128],"conventional":[131,147],"formats.":[132],"However,":[133],"some":[135],"specific":[136],"sizes,":[137],"require":[140],"far":[141],"more":[142],"resources":[143],"than":[144],"corresponding":[146],"approach.":[148]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
