{"id":"https://openalex.org/W2336423189","doi":"https://doi.org/10.1109/tcsii.2016.2557812","title":"Register-Less NULL Convention Logic","display_name":"Register-Less NULL Convention Logic","publication_year":2016,"publication_date":"2016-04-22","ids":{"openalex":"https://openalex.org/W2336423189","doi":"https://doi.org/10.1109/tcsii.2016.2557812","mag":"2336423189"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2016.2557812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2557812","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102063487","display_name":"Meng\u2010Chou Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I70522481","display_name":"National Changhua University of Education","ror":"https://ror.org/005gkfa10","country_code":"TW","type":"education","lineage":["https://openalex.org/I70522481"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Meng-Chou Chang","raw_affiliation_strings":["Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023335089","display_name":"Po-Hung Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I70522481","display_name":"National Changhua University of Education","ror":"https://ror.org/005gkfa10","country_code":"TW","type":"education","lineage":["https://openalex.org/I70522481"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Po-Hung Yang","raw_affiliation_strings":["Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083200361","display_name":"Ze-Gang Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I70522481","display_name":"National Changhua University of Education","ror":"https://ror.org/005gkfa10","country_code":"TW","type":"education","lineage":["https://openalex.org/I70522481"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ze-Gang Pan","raw_affiliation_strings":["Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Engineering, National Changhua University of Education, Changhua, Taiwan","institution_ids":["https://openalex.org/I70522481"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I70522481"],"apc_list":null,"apc_paid":null,"fwci":0.44,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.67477277,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"64","issue":"3","first_page":"314","last_page":"318"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6983625888824463},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6287044286727905},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6161297559738159},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.561485767364502},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4881039559841156},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4576389789581299},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4509267210960388},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.43729496002197266},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4318027198314667},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4120349586009979},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.37977367639541626},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32846108078956604},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21527662873268127},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1685670018196106},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14643949270248413},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08404916524887085},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08311730623245239}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6983625888824463},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6287044286727905},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6161297559738159},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.561485767364502},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4881039559841156},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4576389789581299},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4509267210960388},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.43729496002197266},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4318027198314667},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4120349586009979},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.37977367639541626},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32846108078956604},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21527662873268127},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1685670018196106},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14643949270248413},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08404916524887085},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08311730623245239},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2016.2557812","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2557812","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G7051762558","display_name":"Design of Low-Power Ternary Content-Addressable Memories Using FinFET Devices (II)","funder_award_id":"MOST104-2221-E018-026","funder_id":"https://openalex.org/F4320322795","funder_display_name":"Ministry of Science and Technology, Taiwan"}],"funders":[{"id":"https://openalex.org/F4320322795","display_name":"Ministry of Science and Technology, Taiwan","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W189036309","https://openalex.org/W1565641741","https://openalex.org/W1976222993","https://openalex.org/W1981015639","https://openalex.org/W1985927209","https://openalex.org/W2018430360","https://openalex.org/W2039987950","https://openalex.org/W2064639253","https://openalex.org/W2083794416","https://openalex.org/W2083950284","https://openalex.org/W2103886509","https://openalex.org/W2117299791","https://openalex.org/W2125596564","https://openalex.org/W2160715044","https://openalex.org/W4231670955","https://openalex.org/W6683384013"],"related_works":["https://openalex.org/W2358223609","https://openalex.org/W2371073331","https://openalex.org/W4240239975","https://openalex.org/W2243536805","https://openalex.org/W2356140560","https://openalex.org/W2370649629","https://openalex.org/W2150009275","https://openalex.org/W2770841929","https://openalex.org/W1970702806","https://openalex.org/W2152365648"],"abstract_inverted_index":{"NULL":[0],"Convention":[1],"Logic":[2],"(NCL)":[3],"is":[4],"a":[5],"promising":[6],"design":[7,53],"paradigm":[8,18],"for":[9,22,33,104],"constructing":[10],"low-power":[11],"robust":[12],"asynchronous":[13],"circuits.":[14],"The":[15],"conventional":[16,85],"NCL":[17,44,51,86],"requires":[19],"pipeline":[20,62],"registers":[21,30],"separating":[23],"two":[24],"neighboring":[25],"logic":[26,80],"blocks,":[27],"and":[28,68],"those":[29],"can":[31,98,119],"account":[32],"up":[34],"to":[35,73,112],"35%":[36],"of":[37,42,78,91,124],"the":[38,43,49,65,75,84,88,105,116,121,125],"overall":[39],"power":[40,58,71,77,100],"consumption":[41,59],"circuit.":[45],"This":[46],"brief":[47],"presents":[48],"Register-Less":[50],"(RL-NCL)":[52],"paradigm,":[54],"which":[55],"achieves":[56],"low":[57],"by":[60,102,127],"eliminating":[61],"registers,":[63],"simplifying":[64],"control":[66],"circuit,":[67],"supporting":[69],"fine-grained":[70],"gating":[72],"mitigate":[74],"leakage":[76],"sleeping":[79],"blocks.":[81],"Compared":[82],"with":[83],"counterpart,":[87],"RL-NCL":[89,117],"implementation":[90,118],"an":[92],"8-bit":[93],"five-stage":[94],"pipelined":[95],"Kogge-Stone":[96],"adder":[97,126],"reduce":[99,120],"dissipation":[101],"56.4%-72.5%":[103],"input":[106],"data":[107],"rate":[108],"ranging":[109],"from":[110],"10":[111],"900":[113],"MHz.":[114],"Moreover,":[115],"transistor":[122],"count":[123],"49.5%.":[128]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}