{"id":"https://openalex.org/W2335248059","doi":"https://doi.org/10.1109/tcsii.2016.2551554","title":"MAD Gates\u2014Memristor Logic Design Using Driver Circuitry","display_name":"MAD Gates\u2014Memristor Logic Design Using Driver Circuitry","publication_year":2016,"publication_date":"2016-04-07","ids":{"openalex":"https://openalex.org/W2335248059","doi":"https://doi.org/10.1109/tcsii.2016.2551554","mag":"2335248059"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2016.2551554","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2551554","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063845888","display_name":"Lauren Guckert","orcid":"https://orcid.org/0000-0002-0720-5661"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Lauren Guckert","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":"https://orcid.org/0000-0002-0720-5661","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028439610","display_name":"Earl E. Swartzlander","orcid":"https://orcid.org/0000-0002-8699-5277"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Earl E. Swartzlander","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5063845888"],"corresponding_institution_ids":["https://openalex.org/I86519309"],"apc_list":null,"apc_paid":null,"fwci":5.951,"has_fulltext":false,"cited_by_count":87,"citation_normalized_percentile":{"value":0.96528191,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":"64","issue":"2","first_page":"171","last_page":"175"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.9291248321533203},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7291961908340454},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.656790018081665},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5777210593223572},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.5729097127914429},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.4931163489818573},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.4733959436416626},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4468930661678314},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.4356025457382202},{"id":"https://openalex.org/keywords/xor-gate","display_name":"XOR gate","score":0.43333759903907776},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4218253195285797},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.41037869453430176},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.39451873302459717},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.37885916233062744},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.36625388264656067},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.31017667055130005},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26314759254455566},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2537921965122223},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19969698786735535},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18690606951713562},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16111567616462708},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.15967398881912231},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07736483216285706},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07265210151672363}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.9291248321533203},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7291961908340454},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.656790018081665},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5777210593223572},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.5729097127914429},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.4931163489818573},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.4733959436416626},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4468930661678314},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.4356025457382202},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.43333759903907776},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4218253195285797},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.41037869453430176},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.39451873302459717},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.37885916233062744},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.36625388264656067},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.31017667055130005},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26314759254455566},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2537921965122223},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19969698786735535},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18690606951713562},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16111567616462708},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.15967398881912231},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07736483216285706},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07265210151672363},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2016.2551554","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2016.2551554","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6700000166893005}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1493445957","https://openalex.org/W1578783943","https://openalex.org/W1953553490","https://openalex.org/W1986623396","https://openalex.org/W2004782555","https://openalex.org/W2006221630","https://openalex.org/W2056229294","https://openalex.org/W2058878560","https://openalex.org/W2066280488","https://openalex.org/W2075056947","https://openalex.org/W2075496750","https://openalex.org/W2081729575","https://openalex.org/W2112181056","https://openalex.org/W2117164389","https://openalex.org/W2162651880","https://openalex.org/W2542473330"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W2760452677","https://openalex.org/W2308335786","https://openalex.org/W2127298806","https://openalex.org/W2963778543","https://openalex.org/W2168217865","https://openalex.org/W1979361505","https://openalex.org/W2786283752","https://openalex.org/W2487205419","https://openalex.org/W2133248639"],"abstract_inverted_index":{"Memristors":[0],"have":[1,17],"recently":[2],"begun":[3],"to":[4,74,88,113,143],"be":[5,137],"explored":[6],"in":[7,20],"arithmetic":[8],"applications.":[9],"However,":[10],"all":[11],"prior":[12],"designs":[13],"for":[14,66,78,93],"memristor-based":[15],"gates":[16,112],"had":[18],"shortcomings":[19],"terms":[21],"of":[22,44,59,118,123,132],"scalability,":[23],"applicability,":[24],"completeness,":[25],"and":[26,96,126],"performance.":[27],"In":[28],"this":[29],"brief,":[30],"a":[31,75,115],"new":[32],"low-power":[33],"gate":[34,95],"design,":[35],"i.e.,":[36],"memristors-as-drivers":[37],"gates,":[38],"is":[39,72,86,107],"proposed,":[40,108],"which":[41,109],"overcomes":[42],"each":[43,94],"these":[45,111],"issues":[46],"by":[47],"combining":[48],"sense":[49],"circuitry":[50],"with":[51,120],"the":[52,57,60,64,67,70,133,141],"IMPLY":[53],"operation.":[54],"By":[55],"sensing":[56],"values":[58],"input":[61],"memristors":[62,92,125],"as":[63],"driver":[65],"output":[68],"memristor,":[69],"delay":[71,117],"reduced":[73,87],"single":[76],"step":[77],"any":[79],"Boolean":[80],"operation,":[81],"including":[82],"xor.":[83],"The":[84,129],"area":[85,122],"at":[89],"most":[90],"three":[91],"consumes":[97],"only":[98],"30":[99],"fJ.":[100],"An":[101],"${N}$-bit":[102],"ripple":[103],"carry":[104],"adder":[105,135],"implementation":[106],"uses":[110],"achieve":[114],"total":[116],"${N}+1$":[119],"an":[121],"8${N}$":[124],"their":[127],"drivers.":[128],"individual":[130],"bits":[131],"proposed":[134],"can":[136],"also":[138],"pipelined,":[139],"reducing":[140],"latency":[142],"four":[144],"steps":[145],"per":[146],"addition.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":10},{"year":2022,"cited_by_count":7},{"year":2021,"cited_by_count":14},{"year":2020,"cited_by_count":15},{"year":2019,"cited_by_count":11},{"year":2018,"cited_by_count":9},{"year":2017,"cited_by_count":9},{"year":2016,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}