{"id":"https://openalex.org/W2525256690","doi":"https://doi.org/10.1109/tcsii.2015.2483158","title":"A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM","display_name":"A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM","publication_year":2015,"publication_date":"2015-09-28","ids":{"openalex":"https://openalex.org/W2525256690","doi":"https://doi.org/10.1109/tcsii.2015.2483158","mag":"2525256690"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2015.2483158","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2483158","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108610798","display_name":"Jungtaek You","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jungtaek You","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025679671","display_name":"Junyoung Song","orcid":"https://orcid.org/0000-0002-7994-7234"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Junyoung Song","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100777100","display_name":"Chulwoo Kim","orcid":"https://orcid.org/0000-0003-4379-7905"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chulwoo Kim","raw_affiliation_strings":["Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Engineering, Korea University, Seoul, Korea","institution_ids":["https://openalex.org/I197347611"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I197347611"],"apc_list":null,"apc_paid":null,"fwci":0.2008,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.63284007,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":"64","issue":"10","first_page":"1207","last_page":"1211"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/swing","display_name":"Swing","score":0.7082496285438538},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5303084850311279},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.504238486289978},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5010581016540527},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.48749279975891113},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46985307335853577},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.45453599095344543},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4093194901943207},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3767843544483185},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34728285670280457},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.2889816164970398},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23827850818634033},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2108026146888733},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.19570696353912354},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.1797827184200287},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16167420148849487},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.13441112637519836}],"concepts":[{"id":"https://openalex.org/C65655974","wikidata":"https://www.wikidata.org/wiki/Q14867674","display_name":"Swing","level":2,"score":0.7082496285438538},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5303084850311279},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.504238486289978},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5010581016540527},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.48749279975891113},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46985307335853577},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.45453599095344543},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4093194901943207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3767843544483185},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34728285670280457},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.2889816164970398},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23827850818634033},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2108026146888733},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.19570696353912354},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.1797827184200287},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16167420148849487},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.13441112637519836},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2015.2483158","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2483158","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G6871915530","display_name":null,"funder_award_id":"NRF-2011-0020128","funder_id":"https://openalex.org/F4320322349","funder_display_name":"Ministry of Education, Science and Technology"}],"funders":[{"id":"https://openalex.org/F4320322030","display_name":"Ministry of Science, ICT and Future Planning","ror":"https://ror.org/032e49973"},{"id":"https://openalex.org/F4320322120","display_name":"National Research Foundation of Korea","ror":"https://ror.org/013aysd81"},{"id":"https://openalex.org/F4320322349","display_name":"Ministry of Education, Science and Technology","ror":"https://ror.org/01p262204"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W10143836","https://openalex.org/W1544623790","https://openalex.org/W1607361739","https://openalex.org/W2002743180","https://openalex.org/W2025944889","https://openalex.org/W2089757817","https://openalex.org/W2103692532","https://openalex.org/W2112589346","https://openalex.org/W2117618584","https://openalex.org/W2122219454","https://openalex.org/W2131441996","https://openalex.org/W2141941194","https://openalex.org/W2151817873","https://openalex.org/W2155062435","https://openalex.org/W2177001705","https://openalex.org/W6657011984","https://openalex.org/W6672938105","https://openalex.org/W6677090023"],"related_works":["https://openalex.org/W2360051520","https://openalex.org/W2798244654","https://openalex.org/W3168108534","https://openalex.org/W34871393","https://openalex.org/W4206135463","https://openalex.org/W1486689224","https://openalex.org/W2094697992","https://openalex.org/W2998806118","https://openalex.org/W2118008391","https://openalex.org/W1596579276"],"abstract_inverted_index":{"This":[0],"brief":[1],"proposes":[2],"a":[3,16,35,46],"data-dependent":[4],"swing-limited":[5],"on-chip":[6],"signaling":[7],"for":[8,27],"single-ended":[9],"global":[10,24],"I/O":[11,25],"in":[12,15,34],"the":[13,41,51,57,60,63,66,80,94,97],"SDRAM":[14,21],"0.13-\u03bcm":[17],"CMOS":[18],"technology.":[19],"The":[20,84],"has":[22],"multiple":[23],"lines":[26],"sending":[28],"and":[29,45,53],"receiving":[30],"data,":[31],"which":[32,72],"results":[33],"large":[36,47],"delay":[37,52],"deviation":[38,55],"owing":[39],"to":[40,91],"multi-drop":[42],"bus":[43],"topology":[44],"RC":[48],"load.":[49],"Minimizing":[50],"its":[54],"improves":[56],"speed":[58,68],"of":[59,93],"SDRAM.":[61],"With":[62],"proposed":[64],"technique,":[65],"maximum":[67],"is":[69,73,87,100],"2":[70],"Gb/s/ch,":[71],"increased":[74],"by":[75],"more":[76],"than":[77],"120%":[78],"under":[79],"same":[81],"channel":[82],"condition.":[83],"power":[85],"consumption":[86],"also":[88],"reduced":[89],"compared":[90],"that":[92],"conventional":[95],"scheme;":[96],"energy":[98],"efficiency":[99],"104":[101],"fJ/b/mm,":[102],"respectively.":[103]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}