{"id":"https://openalex.org/W2277822878","doi":"https://doi.org/10.1109/tcsii.2015.2468911","title":"A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%\u201380% Input Duty Cycle for SDRAMs","display_name":"A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%\u201380% Input Duty Cycle for SDRAMs","publication_year":2015,"publication_date":"2015-08-14","ids":{"openalex":"https://openalex.org/W2277822878","doi":"https://doi.org/10.1109/tcsii.2015.2468911","mag":"2277822878"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2015.2468911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2468911","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067863151","display_name":"Ji-Hoon Lim","orcid":"https://orcid.org/0000-0001-7282-7427"},"institutions":[{"id":"https://openalex.org/I123900574","display_name":"Pohang University of Science and Technology","ror":"https://ror.org/04xysgw12","country_code":"KR","type":"education","lineage":["https://openalex.org/I123900574"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Ji-Hoon Lim","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea","institution_ids":["https://openalex.org/I123900574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058398283","display_name":"Jun-Hyun Bae","orcid":"https://orcid.org/0009-0004-0593-5670"},"institutions":[{"id":"https://openalex.org/I123900574","display_name":"Pohang University of Science and Technology","ror":"https://ror.org/04xysgw12","country_code":"KR","type":"education","lineage":["https://openalex.org/I123900574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jun-Hyun Bae","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea","institution_ids":["https://openalex.org/I123900574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101979326","display_name":"Jaemin Jang","orcid":"https://orcid.org/0000-0003-1503-9998"},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaemin Jang","raw_affiliation_strings":["DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea","institution_ids":["https://openalex.org/I134353371"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082816998","display_name":"Hae-Kang Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hae-Kang Jung","raw_affiliation_strings":["DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea","institution_ids":["https://openalex.org/I134353371"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071541267","display_name":"Hyunbae Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyunbae Lee","raw_affiliation_strings":["DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea","institution_ids":["https://openalex.org/I134353371"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008073904","display_name":"Yongju Kim","orcid":"https://orcid.org/0000-0002-5862-5228"},"institutions":[{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yongju Kim","raw_affiliation_strings":["DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, SK Hynix Semiconductor, Icheon, Korea","institution_ids":["https://openalex.org/I134353371"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052722005","display_name":"Byungsub Kim","orcid":"https://orcid.org/0000-0003-1528-6235"},"institutions":[{"id":"https://openalex.org/I123900574","display_name":"Pohang University of Science and Technology","ror":"https://ror.org/04xysgw12","country_code":"KR","type":"education","lineage":["https://openalex.org/I123900574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Byungsub Kim","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea","institution_ids":["https://openalex.org/I123900574"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033088278","display_name":"Jae\u2010Yoon Sim","orcid":"https://orcid.org/0000-0003-1814-6211"},"institutions":[{"id":"https://openalex.org/I123900574","display_name":"Pohang University of Science and Technology","ror":"https://ror.org/04xysgw12","country_code":"KR","type":"education","lineage":["https://openalex.org/I123900574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jae-Yoon Sim","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea","institution_ids":["https://openalex.org/I123900574"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057208951","display_name":"Hong-June Park","orcid":"https://orcid.org/0000-0001-8144-9165"},"institutions":[{"id":"https://openalex.org/I123900574","display_name":"Pohang University of Science and Technology","ror":"https://ror.org/04xysgw12","country_code":"KR","type":"education","lineage":["https://openalex.org/I123900574"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hong-June Park","raw_affiliation_strings":["Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronic and Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, Korea","institution_ids":["https://openalex.org/I123900574"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5067863151"],"corresponding_institution_ids":["https://openalex.org/I123900574"],"apc_list":null,"apc_paid":null,"fwci":1.716,"has_fulltext":false,"cited_by_count":29,"citation_normalized_percentile":{"value":0.83568639,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"63","issue":"2","first_page":"141","last_page":"145"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.7821705341339111},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.5243247747421265},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.5216046571731567},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5057976245880127},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.49084192514419556},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47760459780693054},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.43016839027404785},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.42706137895584106},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.4186493158340454},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38084733486175537},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3240402936935425},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.321756511926651},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3120534121990204},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.29098424315452576},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.26026827096939087},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24678656458854675},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2405456006526947},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.203389972448349}],"concepts":[{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.7821705341339111},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.5243247747421265},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.5216046571731567},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5057976245880127},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.49084192514419556},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47760459780693054},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.43016839027404785},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.42706137895584106},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.4186493158340454},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38084733486175537},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3240402936935425},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.321756511926651},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3120534121990204},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.29098424315452576},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.26026827096939087},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24678656458854675},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2405456006526947},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.203389972448349},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsii.2015.2468911","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2468911","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:oasis.postech.ac.kr:2014.oak/35984","is_oa":false,"landing_page_url":"https://oasis.postech.ac.kr/handle/2014.oak/35984","pdf_url":null,"source":{"id":"https://openalex.org/S4306401965","display_name":"Open Access System for Information Sharing (Pohang University of Science and Technology)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I123900574","host_organization_name":"Pohang University of Science and Technology","host_organization_lineage":["https://openalex.org/I123900574"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7699999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1540664825","https://openalex.org/W1969806930","https://openalex.org/W1978346157","https://openalex.org/W1986524857","https://openalex.org/W1990497714","https://openalex.org/W2052293768","https://openalex.org/W2092075230","https://openalex.org/W2126227985","https://openalex.org/W2128571955","https://openalex.org/W6644616491","https://openalex.org/W6673541384"],"related_works":["https://openalex.org/W114500912","https://openalex.org/W2898479400","https://openalex.org/W1502047864","https://openalex.org/W2735947162","https://openalex.org/W2066428821","https://openalex.org/W3149081039","https://openalex.org/W2144109350","https://openalex.org/W1965937483","https://openalex.org/W25960601","https://openalex.org/W2538145505"],"abstract_inverted_index":{"A":[0,72],"feedback":[1,27,61],"edge":[2,28,33,41,50,58],"combiner":[3,29],"is":[4,64,79,91,191,200],"proposed":[5],"for":[6,81],"the":[7,19,31,39,48,52,56,69,89,98,123,138,142,146,152,175],"duty-cycle":[8],"corrector":[9],"(DCC)":[10],"of":[11,21,34,42,51,59,68,88,100,122,125,162],"a":[12,35,60,65,108,114],"delay":[13,76,104,117,129],"locked":[14],"loop":[15],"(DLL)":[16],"to":[17,156,181],"increase":[18],"range":[20,153,178],"allowed":[22,147],"input":[23,44,148],"duty":[24,149],"cycle.":[25],"The":[26,85,135,187,197],"generates":[30,47],"rising":[32,40,57],"DCC":[36,53,70],"output":[37,54],"at":[38,55,168,184,194],"an":[43,133],"clock.":[45],"It":[46],"falling":[49],"clock":[62],"that":[63],"half-period-delayed":[66],"signal":[67],"output.":[71],"dual-delay-line":[73],"digitally":[74],"controlled":[75],"line":[77,118],"(DCDL)":[78],"used":[80],"seamless":[82],"boundary":[83],"switching.":[84],"chip":[86,139,198],"area":[87,199],"DCDL":[90],"reduced":[92],"by":[93,96,107,132],"around":[94],"46%":[95],"employing":[97],"architecture":[99,124],"two":[101,126],"short":[102],"coarse":[103,116,128],"lines":[105,130],"followed":[106,131],"fine":[109],"phase":[110],"mixer":[111],"(FPM)":[112],"and":[113,159,164,171,174],"long":[115,127],"in":[119,141,151],"series":[120],"instead":[121],"FPM.":[134],"measurements":[136],"on":[137],"fabricated":[140],"65-nm":[143],"CMOS":[144],"show":[145],"cycle":[150],"from":[154,179],"20%":[155],"80%;":[157],"root-mean-square":[158],"peak-to-peak":[160],"jitters":[161],"2.69":[163],"14.0":[165],"ps,":[166],"respectively,":[167],"2":[169],"GHz":[170,183],"1.2":[172,185,195],"V;":[173],"operating":[176],"frequency":[177],"0.12":[180],"2.0":[182],"V.":[186,196],"measured":[188],"power":[189],"consumption":[190],"3.3":[192],"mW/GHz":[193],"0.059":[201],"mm":[202],"<sup":[203],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[204],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[205],".":[206]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}