{"id":"https://openalex.org/W1900581454","doi":"https://doi.org/10.1109/tcsii.2015.2456111","title":"All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM","display_name":"All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM","publication_year":2015,"publication_date":"2015-07-14","ids":{"openalex":"https://openalex.org/W1900581454","doi":"https://doi.org/10.1109/tcsii.2015.2456111","mag":"1900581454"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2015.2456111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2456111","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077472696","display_name":"Young-Jae An","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Young-Jae An","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":"https://orcid.org/0000-0002-0354-4797"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]},{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Samsung Electronics Company, Ltd., Yongin, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Samsung Electronics Company, Ltd., Yongin, Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jung-Hyun Park","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jung-Hyun Park","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109424862","display_name":"Seong-Ook Jung","orcid":"https://orcid.org/0000-0002-5720-4149"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.6067,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.85054386,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"62","issue":"11","first_page":"1023","last_page":"1027"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.9018333554267883},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7839691042900085},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.6884133815765381},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5086177587509155},{"id":"https://openalex.org/keywords/replica","display_name":"Replica","score":0.47679781913757324},{"id":"https://openalex.org/keywords/phase-locking","display_name":"Phase locking","score":0.43418434262275696},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.4181773066520691},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.41237717866897583},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3984752595424652},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.34301626682281494},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.29269105195999146},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.27216148376464844},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2633121907711029},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20083105564117432},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13731074333190918}],"concepts":[{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.9018333554267883},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7839691042900085},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.6884133815765381},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5086177587509155},{"id":"https://openalex.org/C2775937380","wikidata":"https://www.wikidata.org/wiki/Q1232589","display_name":"Replica","level":2,"score":0.47679781913757324},{"id":"https://openalex.org/C2989183493","wikidata":"https://www.wikidata.org/wiki/Q2040587","display_name":"Phase locking","level":3,"score":0.43418434262275696},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.4181773066520691},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.41237717866897583},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3984752595424652},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.34301626682281494},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.29269105195999146},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.27216148376464844},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2633121907711029},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20083105564117432},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13731074333190918},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C78434282","wikidata":"https://www.wikidata.org/wiki/Q11656","display_name":"Diode","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2015.2456111","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2015.2456111","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[{"id":"https://openalex.org/G2250690448","display_name":null,"funder_award_id":"10050534","funder_id":"https://openalex.org/F4320321681","funder_display_name":"Ministry of Trade, Industry and Energy"}],"funders":[{"id":"https://openalex.org/F4320321681","display_name":"Ministry of Trade, Industry and Energy","ror":"https://ror.org/008nkqk13"},{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2039610459","https://openalex.org/W2044230919","https://openalex.org/W2052293768","https://openalex.org/W2066428821","https://openalex.org/W2103011017","https://openalex.org/W2110921254","https://openalex.org/W2126227985","https://openalex.org/W2132455089","https://openalex.org/W2144572765"],"related_works":["https://openalex.org/W2354050524","https://openalex.org/W2401743820","https://openalex.org/W3177439118","https://openalex.org/W2083878249","https://openalex.org/W4295813049","https://openalex.org/W2119216036","https://openalex.org/W2389594899","https://openalex.org/W2976219355","https://openalex.org/W2900271051","https://openalex.org/W766471173"],"abstract_inverted_index":{"A":[0,19],"fast-locking":[1,74],"all-digital":[2],"delay-locked":[3],"loop":[4,22,44,51],"(DLL)":[5],"with":[6],"closed-loop":[7],"duty-cycle":[8],"correction":[9],"(DCC)":[10],"capability":[11],"is":[12,23,63,85,114,120],"proposed":[13,24,42,61,83],"for":[14,53],"clock":[15],"synchronization":[16],"in":[17,38,126],"DRAM.":[18],"new":[20],"cyclic-locking":[21],"to":[25,32,70,140],"resolve":[26],"the":[27,33,39,60,144],"locking":[28,57,135],"speed":[29],"degradation":[30],"due":[31],"replica":[34],"delay":[35,52],"line":[36],"(RDL)":[37],"DLL.":[40],"The":[41,56,82,110,133],"cycliclocking":[43],"operates":[45],"asynchronously":[46],"and":[47,104,117],"offers":[48],"an":[49,93],"optimal":[50],"DLL":[54,62,84],"locking.":[55],"time":[58,136],"of":[59,72,96,130],"decreased":[64],"by":[65],"more":[66],"than":[67],"34.1%":[68],"compared":[69],"that":[71],"previous":[73],"DLLs":[75],"using":[76,87],"a":[77,106,127],"successive":[78],"approximation":[79],"register":[80],"algorithm.":[81],"fabricated":[86],"65-nm":[88],"CMOS":[89],"process":[90],"technology":[91],"on":[92],"active":[94],"area":[95],"465.1":[97],"\u00d7":[98],"37":[99],"\u03bcm":[100],"<sup":[101],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[102],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[103],"uses":[105],"1.1-V":[107],"supply":[108],"voltage.":[109],"operating":[111,146],"frequency":[112,147],"range":[113],"400-800":[115],"MHz,":[116,124],"3.52":[118],"mW":[119],"consumed":[121],"at":[122],"800":[123],"resulting":[125],"power":[128],"consumption":[129],"4.4":[131],"pJ/Hz.":[132],"measured":[134],"ranges":[137],"from":[138],"38":[139],"41":[141],"cycles":[142],"over":[143],"entire":[145],"range.":[148]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
