{"id":"https://openalex.org/W2052293768","doi":"https://doi.org/10.1109/tcsii.2013.2291052","title":"Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector","display_name":"Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2052293768","doi":"https://doi.org/10.1109/tcsii.2013.2291052","mag":"2052293768"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2013.2291052","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2013.2291052","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":"https://orcid.org/0000-0002-0354-4797"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":3.4069,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.93151889,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"61","issue":"1","first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7804076671600342},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.7062230706214905},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.593116819858551},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5667523145675659},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5384189486503601},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5001208782196045},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4519653916358948},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.45131754875183105},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.44796091318130493},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4355594217777252},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37603825330734253},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3395114839076996},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18176418542861938},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1764099895954132},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15092328190803528},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11763879656791687},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08529570698738098},{"id":"https://openalex.org/keywords/control","display_name":"Control (management)","score":0.07379725575447083},{"id":"https://openalex.org/keywords/control-engineering","display_name":"Control engineering","score":0.07369813323020935}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7804076671600342},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.7062230706214905},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.593116819858551},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5667523145675659},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5384189486503601},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5001208782196045},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4519653916358948},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.45131754875183105},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.44796091318130493},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4355594217777252},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37603825330734253},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3395114839076996},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18176418542861938},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1764099895954132},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15092328190803528},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11763879656791687},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08529570698738098},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.07379725575447083},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.07369813323020935},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2013.2291052","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2013.2291052","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1997549152","https://openalex.org/W2021452744","https://openalex.org/W2043037338","https://openalex.org/W2043584381","https://openalex.org/W2065318410","https://openalex.org/W2106042087","https://openalex.org/W2110921254","https://openalex.org/W2126227985","https://openalex.org/W6661353760"],"related_works":["https://openalex.org/W1488060887","https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2043945969","https://openalex.org/W2103754166","https://openalex.org/W2139484866","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W3113661469"],"abstract_inverted_index":{"A":[0],"multiphase":[1],"delay":[2,50],"locked":[3],"loop":[4],"(DLL)":[5],"that":[6],"can":[7],"calibrate":[8],"the":[9,14,19,23,36,44,105,110],"interphase":[10],"error":[11,46,117,127],"and":[12,73,79,123],"guarantee":[13],"50%":[15],"duty":[16,64,125],"cycle":[17,65,126],"of":[18,22,118,128],"output":[20],"clock":[21],"DLL":[24,95,112],"is":[25,33,67,87,96],"presented.":[26],"The":[27,93],"proposed":[28,88,94,111],"process":[29],"variation":[30],"calibration":[31],"architecture":[32],"implemented":[34,68],"without":[35],"need":[37],"for":[38,89],"complex":[39],"circuitry":[40],"because":[41],"it":[42],"calibrates":[43],"phase":[45,85,116],"using":[47,98],"a":[48,62,83,99,114,124],"simple":[49],"averaging":[51],"operation":[52],"among":[53],"four":[54],"90":[55],"<sup":[56,120],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[57,121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\u00b0</sup>":[58,122],"shifters.":[59],"In":[60],"addition,":[61],"loop-embedded":[63],"corrector":[66],"with":[69],"extremely":[70],"small":[71],"power":[72],"area":[74],"requirements":[75],"by":[76],"adopting":[77],"feedforward":[78],"feedback":[80],"paths.":[81],"Finally,":[82],"sense-amplifier-based":[84],"detector":[86],"reducing":[90],"dithering":[91],"jitter.":[92],"fabricated":[97],"0.13-":[100],"\u03bcm":[101],"CMOS":[102],"process.":[103],"For":[104],"seven":[106],"test":[107],"chips":[108],"analyzed,":[109],"had":[113],"maximum":[115],"1.8":[119],"0.97%":[129],"at":[130],"800":[131],"MHz.":[132]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}