{"id":"https://openalex.org/W2089684280","doi":"https://doi.org/10.1109/tcsii.2013.2278123","title":"A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology","display_name":"A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology","publication_year":2013,"publication_date":"2013-08-29","ids":{"openalex":"https://openalex.org/W2089684280","doi":"https://doi.org/10.1109/tcsii.2013.2278123","mag":"2089684280"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2013.2278123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2013.2278123","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050298468","display_name":"Sebastian H\u00f6ppner","orcid":"https://orcid.org/0000-0002-9938-2736"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Hoppner","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032538320","display_name":"Stefan Haenzsche","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Stefan Haenzsche","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059380044","display_name":"Georg Ellguth","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Georg Ellguth","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091157874","display_name":"Dennis Walter","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dennis Walter","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015001805","display_name":"Holger Eisenreich","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Holger Eisenreich","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046407","display_name":"Ren\u00e9 Sch\u00fcffny","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rene Schuffny","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Fac. of Electr. & Comput. Eng., Tech. Univ. Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":5.8717,"has_fulltext":false,"cited_by_count":50,"citation_normalized_percentile":{"value":0.96539844,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"60","issue":"11","first_page":"741","last_page":"745"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8943098783493042},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8153146505355835},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7785176038742065},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.6889907717704773},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5915787816047668},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5769551992416382},{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.5477664470672607},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.469585120677948},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4647241234779358},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4557582437992096},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.38944607973098755},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3160158395767212},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29865217208862305},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.18037396669387817},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.14822539687156677}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8943098783493042},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8153146505355835},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7785176038742065},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.6889907717704773},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5915787816047668},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5769551992416382},{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.5477664470672607},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.469585120677948},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4647241234779358},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4557582437992096},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.38944607973098755},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3160158395767212},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29865217208862305},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.18037396669387817},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.14822539687156677},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2013.2278123","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2013.2278123","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1975856998","https://openalex.org/W2009388165","https://openalex.org/W2017690880","https://openalex.org/W2038714764","https://openalex.org/W2090963250","https://openalex.org/W2112008043","https://openalex.org/W2119080246","https://openalex.org/W2119143324","https://openalex.org/W2145442218","https://openalex.org/W2147460185","https://openalex.org/W2154332266","https://openalex.org/W2536897938","https://openalex.org/W6673266725","https://openalex.org/W6676844732","https://openalex.org/W6681530876"],"related_works":["https://openalex.org/W2139484866","https://openalex.org/W2936029881","https://openalex.org/W2301158783","https://openalex.org/W2072077388","https://openalex.org/W2369998856","https://openalex.org/W2133120878","https://openalex.org/W1969806930","https://openalex.org/W2002107209","https://openalex.org/W2376956425","https://openalex.org/W1984967896"],"abstract_inverted_index":{"This":[0,35],"brief":[1],"presents":[2],"a":[3,24,62,102],"bang-bang":[4],"all-digital":[5],"phase-locked":[6],"loop":[7],"(ADPLL)":[8],"clock":[9],"generator":[10],"for":[11,29,39],"multiprocessor":[12],"system-on-chip":[13],"applications":[14],"in":[15,46],"Globalfoundries":[16],"28-nm":[17],"superlow-power":[18],"CMOS":[19],"technology.":[20],"The":[21,59],"circuit":[22],"features":[23],"single-shot":[25],"phase":[26,31],"synchronization":[27],"scheme":[28],"instantaneous":[30,57],"lock":[32,51],"after":[33],"power-up.":[34],"feature":[36],"is":[37],"used":[38],"fast":[40],"frequency":[41],"search":[42],"during":[43],"lock-in,":[44],"resulting":[45],"less":[47],"than":[48],"1-\u03bcs":[49],"initial":[50],"time":[52],"and":[53,74,97],"the":[54],"capability":[55],"of":[56,65,90],"restart.":[58],"ADPLL":[60],"provides":[61],"wide":[63],"range":[64],"output":[66],"clocks":[67],"from":[68,101],"83":[69],"MHz":[70],"to":[71],"2":[72,84],"GHz":[73],"exhibits":[75],"31-ps":[76],"accumulated":[77],"jitter":[78,82],"with":[79],"3-ps":[80],"period":[81],"at":[83],"GHz.":[85],"It":[86],"occupies":[87],"an":[88],"area":[89],"only":[91],"0.00234":[92],"mm":[93],"<sup":[94],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[95],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[96],"consumes":[98],"0.64":[99],"mW":[100],"1.0-V":[103],"supply.":[104]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":6},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":4},{"year":2016,"cited_by_count":12},{"year":2015,"cited_by_count":10},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}