{"id":"https://openalex.org/W2119304228","doi":"https://doi.org/10.1109/tcsii.2009.2034198","title":"Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment","display_name":"Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment","publication_year":2009,"publication_date":"2009-11-20","ids":{"openalex":"https://openalex.org/W2119304228","doi":"https://doi.org/10.1109/tcsii.2009.2034198","mag":"2119304228"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2009.2034198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2034198","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088586836","display_name":"Shen\u2010Fu Hsiao","orcid":"https://orcid.org/0000-0002-4627-570X"},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shen-Fu Hsiao","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111671804","display_name":"Ming-Yu Tsai","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ming-Yu Tsai","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008742070","display_name":"Chia-Sheng Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I142974352","display_name":"National Sun Yat-sen University","ror":"https://ror.org/00mjawt10","country_code":"TW","type":"education","lineage":["https://openalex.org/I142974352"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Sheng Wen","raw_affiliation_strings":["Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, National Sun Yat-sen University,  Kaohsiung, Taiwan","institution_ids":["https://openalex.org/I142974352"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I142974352"],"apc_list":null,"apc_paid":null,"fwci":0.6005,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.72486229,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"57","issue":"1","first_page":"21","last_page":"25"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6822918057441711},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.601189136505127},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5273324251174927},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.505924642086029},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.49883484840393066},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4200356602668762},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4092632234096527},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30189943313598633},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2663939893245697},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.15712043642997742},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10908520221710205},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08469271659851074}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6822918057441711},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.601189136505127},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5273324251174927},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.505924642086029},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.49883484840393066},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4200356602668762},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4092632234096527},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30189943313598633},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2663939893245697},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.15712043642997742},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10908520221710205},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08469271659851074},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2009.2034198","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2034198","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.46000000834465027}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W2000787196","https://openalex.org/W2030029202","https://openalex.org/W2124278579","https://openalex.org/W2129042422","https://openalex.org/W2129926968","https://openalex.org/W2135955108","https://openalex.org/W2139166362","https://openalex.org/W2141849037","https://openalex.org/W2152216926","https://openalex.org/W2156028445","https://openalex.org/W2166895905","https://openalex.org/W2169260669","https://openalex.org/W3150081868","https://openalex.org/W6650739249","https://openalex.org/W6684844013"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W1900707063","https://openalex.org/W2109445684","https://openalex.org/W2164005033","https://openalex.org/W2170979950","https://openalex.org/W98108296","https://openalex.org/W4297984620","https://openalex.org/W2542018869"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"a":[3,61],"logic":[4,17,31,35,40,54],"synthesis":[5,41],"flow":[6],"that":[7],"depends":[8],"on":[9,22,74],"the":[10,23,75],"popular":[11],"Synopsys":[12],"Design":[13],"Compiler":[14],"to":[15],"perform":[16],"translation":[18],"and":[19,33,101],"minimization":[20],"based":[21,73],"standard":[24,76],"cell":[25,77],"library":[26,78],"with":[27,67,79],"both":[28],"pass":[29],"transistor":[30],"(PTL)":[32],"CMOS":[34,104],"cells.":[36,64,87],"The":[37,50],"hybrid":[38,85],"PTL/CMOS":[39,86],"can":[42],"generate":[43],"appropriate":[44],"circuits":[45,97],"considering":[46],"various":[47],"design":[48],"constraints.":[49],"proposed":[51],"multilevel":[52],"PTL":[53,96],"cells":[55],"are":[56,71],"automatically":[57],"constructed":[58],"from":[59],"only":[60],"few":[62],"basic":[63],"Postlayout":[65],"simulations":[66],"UMC":[68],"90-nm":[69],"technology":[70],"presented":[72],"pure":[80,82,95],"PTL,":[81],"CMOS,":[83],"or":[84],"Experimental":[88],"results":[89],"show":[90],"that,":[91],"in":[92,106],"most":[93],"cases,":[94],"have":[98,108],"smaller":[99,109],"area":[100],"power,":[102],"whereas":[103],"circuits,":[105],"general,":[107],"delay.":[110]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
