{"id":"https://openalex.org/W2148865862","doi":"https://doi.org/10.1109/tcsii.2009.2034079","title":"A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming","display_name":"A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming","publication_year":2009,"publication_date":"2009-11-01","ids":{"openalex":"https://openalex.org/W2148865862","doi":"https://doi.org/10.1109/tcsii.2009.2034079","mag":"2148865862"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2009.2034079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2034079","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110253245","display_name":"Stefan Mendel","orcid":null},"institutions":[{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"S. Mendel","raw_affiliation_strings":["Signal Processing and Speech Communication Laboratory, Graz University of Technology, Graz, Austria"],"affiliations":[{"raw_affiliation_string":"Signal Processing and Speech Communication Laboratory, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077070239","display_name":"Christian Vogel","orcid":"https://orcid.org/0000-0002-8617-5375"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]},{"id":"https://openalex.org/I4092182","display_name":"Graz University of Technology","ror":"https://ror.org/00d7xrm67","country_code":"AT","type":"education","lineage":["https://openalex.org/I4092182"]}],"countries":["AT","CH"],"is_corresponding":false,"raw_author_name":"C. Vogel","raw_affiliation_strings":["Signal Processing and Speech Communication Laboratory, Graz University of Technology, Graz, Austria","Signal and Information Processing Laboratory, Swiss Federal Institute of Technology of Z\u00fcrich, Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Signal Processing and Speech Communication Laboratory, Graz University of Technology, Graz, Austria","institution_ids":["https://openalex.org/I4092182"]},{"raw_affiliation_string":"Signal and Information Processing Laboratory, Swiss Federal Institute of Technology of Z\u00fcrich, Zurich, Switzerland","institution_ids":["https://openalex.org/I5124864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111819598","display_name":"Nicola Da Dalt","orcid":null},"institutions":[{"id":"https://openalex.org/I4210131793","display_name":"Infineon Technologies (Austria)","ror":"https://ror.org/03msng824","country_code":"AT","type":"company","lineage":["https://openalex.org/I137594350","https://openalex.org/I4210131793"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"N. Da Dalt","raw_affiliation_strings":["Infineon Technologies Development Center, Villach, Austria"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies Development Center, Villach, Austria","institution_ids":["https://openalex.org/I4210131793"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110253245"],"corresponding_institution_ids":["https://openalex.org/I4092182"],"apc_list":null,"apc_paid":null,"fwci":2.4385,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.89583764,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":"56","issue":"11","first_page":"860","last_page":"864"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.9604836702346802},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.6205366849899292},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6171120405197144},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5907213091850281},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5892208814620972},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5185935497283936},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.47921448945999146},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47753632068634033},{"id":"https://openalex.org/keywords/digitally-controlled-oscillator","display_name":"Digitally controlled oscillator","score":0.4649896025657654},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.42538073658943176},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.41785943508148193},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2267550528049469},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14074471592903137},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12471109628677368},{"id":"https://openalex.org/keywords/delay-line-oscillator","display_name":"Delay line oscillator","score":0.11082577705383301},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.08408090472221375}],"concepts":[{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.9604836702346802},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.6205366849899292},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6171120405197144},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5907213091850281},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5892208814620972},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5185935497283936},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.47921448945999146},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47753632068634033},{"id":"https://openalex.org/C167872736","wikidata":"https://www.wikidata.org/wiki/Q5276224","display_name":"Digitally controlled oscillator","level":5,"score":0.4649896025657654},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.42538073658943176},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.41785943508148193},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2267550528049469},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14074471592903137},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12471109628677368},{"id":"https://openalex.org/C26907483","wikidata":"https://www.wikidata.org/wiki/Q5253479","display_name":"Delay line oscillator","level":4,"score":0.11082577705383301},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.08408090472221375}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcsii.2009.2034079","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2034079","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.212.9493","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.212.9493","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www2.spsc.tugraz.at/people/cvogel/Papers/2009_vogelTCASII.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.468.7596","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.468.7596","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://userver.ftw.at/~vogel/Papers/2009_vogelTCASII.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1544882865","https://openalex.org/W1578889014","https://openalex.org/W2084208879","https://openalex.org/W2103868891","https://openalex.org/W2155863472","https://openalex.org/W2161473815","https://openalex.org/W2164582257","https://openalex.org/W2171301964","https://openalex.org/W6683986549"],"related_works":["https://openalex.org/W2124909075","https://openalex.org/W2169622190","https://openalex.org/W1607003253","https://openalex.org/W2224788396","https://openalex.org/W2117541676","https://openalex.org/W2169618112","https://openalex.org/W2118205354","https://openalex.org/W2151256709","https://openalex.org/W4238381000","https://openalex.org/W2148865862"],"abstract_inverted_index":{"<para":[0],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[1],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[2],"State-of-the-art":[3],"phase-domain":[4],"all-digital":[5],"phase-locked":[6],"loops":[7],"(ADPLLs)":[8],"require":[9],"a":[10,36,79,104],"retimed":[11,56],"reference":[12,25,57,106,129],"clock":[13,26],"to":[14,41],"synchronize":[15],"the":[16,24,29,45,52,55,63,75,93,97,117,122,126],"digitally":[17],"controlled":[18],"oscillator":[19],"(DCO)":[20],"output":[21,47],"frequency":[22,48],"and":[23,73,85,108,120],"frequency.":[27],"Therefore,":[28],"entire":[30,98],"digital":[31],"logic":[32],"is":[33,49],"operated":[34],"with":[35,51,103],"periodically":[37],"nonuniform":[38],"clock.":[39],"Due":[40],"on-chip":[42],"coupling":[43],"effects,":[44],"DCO":[46],"pulled":[50],"edges":[53],"of":[54,83,125],"clock,":[58,107],"producing":[59],"undesired":[60],"spurs":[61,111],"in":[62],"phase":[64],"noise":[65],"power":[66],"spectrum.":[67],"In":[68],"this":[69],"brief,":[70],"we":[71],"analyze":[72],"classify":[74],"spur":[76,118],"generation":[77],"from":[78],"signal":[80],"processing":[81],"point":[82],"view":[84],"propose":[86],"an":[87],"alternative":[88],"ADPLL":[89,99],"implementation":[90],"that":[91],"abandons":[92],"retiming":[94],"mechanism.":[95],"Thus,":[96],"can":[100],"be":[101],"clocked":[102],"uniform":[105],"consequently,":[109],"side":[110],"are":[112],"avoided.":[113],"Behavioral":[114],"simulations":[115],"verify":[116],"analysis":[119],"emphasize":[121],"improved":[123],"behavior":[124],"proposed":[127],"synchronous":[128],"architecture.":[130],"</para>":[131]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":4}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
