{"id":"https://openalex.org/W4246775661","doi":"https://doi.org/10.1109/tcsii.2009.2024245","title":"Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction","display_name":"Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W4246775661","doi":"https://doi.org/10.1109/tcsii.2009.2024245"},"language":"en","primary_location":{"id":"doi:10.1109/tcsii.2009.2024245","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2024245","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038283352","display_name":"C.C. Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I1343871089","display_name":"Los Alamos National Laboratory","ror":"https://ror.org/01e41cf67","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I1343871089","https://openalex.org/I198811213","https://openalex.org/I4210120050"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"C.C. Wang","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Los Alamos, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Los Alamos, CA, USA","institution_ids":["https://openalex.org/I1343871089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003700236","display_name":"Dejan Markovi\u0107","orcid":"https://orcid.org/0000-0002-6744-7531"},"institutions":[{"id":"https://openalex.org/I1343871089","display_name":"Los Alamos National Laboratory","ror":"https://ror.org/01e41cf67","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I1343871089","https://openalex.org/I198811213","https://openalex.org/I4210120050"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Markovic","raw_affiliation_strings":["Department of Electrical Engineering, University of California, Los Alamos, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of California, Los Alamos, CA, USA","institution_ids":["https://openalex.org/I1343871089"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038283352"],"corresponding_institution_ids":["https://openalex.org/I1343871089"],"apc_list":null,"apc_paid":null,"fwci":1.1963,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.82216127,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"56","issue":"8","first_page":"634","last_page":"638"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.826849102973938},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7405514717102051},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.610102117061615},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.5686490535736084},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5032920241355896},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45727163553237915},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4408970773220062},{"id":"https://openalex.org/keywords/logical-conjunction","display_name":"Logical conjunction","score":0.43628567457199097},{"id":"https://openalex.org/keywords/and-gate","display_name":"AND gate","score":0.4339807629585266},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4280085563659668},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.38815703988075256},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36035647988319397},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24438399076461792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13842448592185974},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11897420883178711},{"id":"https://openalex.org/keywords/chemistry","display_name":"Chemistry","score":0.08268770575523376}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.826849102973938},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7405514717102051},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.610102117061615},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.5686490535736084},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5032920241355896},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45727163553237915},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4408970773220062},{"id":"https://openalex.org/C21847791","wikidata":"https://www.wikidata.org/wiki/Q191081","display_name":"Logical conjunction","level":2,"score":0.43628567457199097},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.4339807629585266},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4280085563659668},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.38815703988075256},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36035647988319397},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24438399076461792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13842448592185974},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11897420883178711},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.08268770575523376},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C178790620","wikidata":"https://www.wikidata.org/wiki/Q11351","display_name":"Organic chemistry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsii.2009.2024245","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsii.2009.2024245","pdf_url":null,"source":{"id":"https://openalex.org/S93916849","display_name":"IEEE Transactions on Circuits & Systems II Express Briefs","issn_l":"1549-7747","issn":["1549-7747","1558-3791"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems II: Express Briefs","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2088115909","https://openalex.org/W2109913853","https://openalex.org/W2117927146","https://openalex.org/W2125778215","https://openalex.org/W2133896241","https://openalex.org/W2134067926","https://openalex.org/W2142100344","https://openalex.org/W2149622198","https://openalex.org/W2153090913","https://openalex.org/W2153677786","https://openalex.org/W2154930846","https://openalex.org/W6682009686"],"related_works":["https://openalex.org/W2909211499","https://openalex.org/W3119688974","https://openalex.org/W2060067973","https://openalex.org/W4321519815","https://openalex.org/W2762653771","https://openalex.org/W1967469573","https://openalex.org/W2285967966","https://openalex.org/W2329911060","https://openalex.org/W2912276428","https://openalex.org/W2049650033"],"abstract_inverted_index":{"This":[0],"brief":[1],"presents":[2],"an":[3,84],"improved":[4],"logical-effort":[5,109],"model":[6,22,50,110],"to":[7,60,82,120],"account":[8],"for":[9,39,95],"the":[10,14,36,49,68,96,101,107,112],"slope":[11],"mismatch":[12],"between":[13,67],"input":[15,69],"and":[16,44,70,111,122],"output":[17,71],"of":[18,104,118],"a":[19,24,76,88],"gate.":[20],"The":[21,92],"has":[23],"simple":[25],"formulation":[26],"in":[27,56],"which":[28],"only":[29],"one":[30],"additional":[31],"parameter":[32],"is":[33,80,98],"needed,":[34],"making":[35],"analysis":[37],"suitable":[38],"hand":[40],"calculations.":[41],"Using":[42,73],"65-":[43],"90-nm":[45],"complementary":[46],"metal-oxide-semiconductor":[47],"technologies,":[48],"maintains":[51],"less":[52],"than":[53],"5%":[54],"error":[55,94],"gate-delay":[57],"estimations":[58],"compared":[59],"Spectre":[61],"simulations":[62],"even":[63],"under":[64],"large":[65],"variations":[66],"slopes.":[72],"this":[74],"model,":[75],"circuit":[77],"optimization":[78],"tool":[79],"written":[81],"optimize":[83],"adder":[85,97],"synthesized":[86],"with":[87],"65-nm":[89],"standard-cell":[90],"library.":[91],"estimation":[93],"also":[99],"within":[100],"modeling":[102],"accuracy":[103],"5%,":[105],"whereas":[106],"original":[108],"synthesis":[113],"timing":[114],"libraries":[115],"have":[116],"errors":[117],"up":[119],"40%":[121],"20%,":[123],"respectively.":[124]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2020,"cited_by_count":3},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
