{"id":"https://openalex.org/W7131656287","doi":"https://doi.org/10.1109/tcsi.2026.3662461","title":"A Low-Latency Synchronization Header Detector and Hardware-Efficient Correction Decoder for JESD204C Receiver","display_name":"A Low-Latency Synchronization Header Detector and Hardware-Efficient Correction Decoder for JESD204C Receiver","publication_year":2026,"publication_date":"2026-02-26","ids":{"openalex":"https://openalex.org/W7131656287","doi":"https://doi.org/10.1109/tcsi.2026.3662461"},"language":null,"primary_location":{"id":"doi:10.1109/tcsi.2026.3662461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2026.3662461","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031966298","display_name":"Peng Yin","orcid":"https://orcid.org/0000-0001-5422-653X"},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Peng Yin","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":"https://orcid.org/0000-0001-5422-653X","affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126861049","display_name":"Haoran Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haoran Chen","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026485724","display_name":"R. Q.","orcid":null},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rui Ma","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":"https://orcid.org/0000-0003-0512-8751","affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jinlong Zhang","orcid":"https://orcid.org/0000-0003-2617-1986"},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jinlong Zhang","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":"https://orcid.org/0000-0003-2617-1986","affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5126934749","display_name":"Mingguo Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Mingguo Liu","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026742117","display_name":"Weizhou Hou","orcid":null},"institutions":[{"id":"https://openalex.org/I173899330","display_name":"Henan University","ror":"https://ror.org/003xyzq10","country_code":"CN","type":"education","lineage":["https://openalex.org/I173899330"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weizhou Hou","raw_affiliation_strings":["School of Physics and Electronics, Henan University (HENU), Kaifeng, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Physics and Electronics, Henan University (HENU), Kaifeng, China","institution_ids":["https://openalex.org/I173899330"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5122230534","display_name":"Shubin Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I55712492","display_name":"Zhejiang University of Technology","ror":"https://ror.org/02djqfd08","country_code":"CN","type":"education","lineage":["https://openalex.org/I55712492"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-9942-0069","affiliations":[{"raw_affiliation_string":"Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China","institution_ids":["https://openalex.org/I55712492"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121677025","display_name":"Zhou Shu","orcid":null},"institutions":[{"id":"https://openalex.org/I55712492","display_name":"Zhejiang University of Technology","ror":"https://ror.org/02djqfd08","country_code":"CN","type":"education","lineage":["https://openalex.org/I55712492"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhou Shu","raw_affiliation_strings":["Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0003-0976-1263","affiliations":[{"raw_affiliation_string":"Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China","institution_ids":["https://openalex.org/I55712492"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5126928724","display_name":"Zhangming Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I55712492","display_name":"Zhejiang University of Technology","ror":"https://ror.org/02djqfd08","country_code":"CN","type":"education","lineage":["https://openalex.org/I55712492"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China"],"raw_orcid":"https://orcid.org/0000-0002-7764-1928","affiliations":[{"raw_affiliation_string":"Zhejiang Key Laboratory of Analog Integrated Circuits, Hangzhou Institute of Technology, Hangzhou, China","institution_ids":["https://openalex.org/I55712492"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17472515,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"73","issue":"7","first_page":"4916","last_page":"4928"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.29670000076293945,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.29670000076293945,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.0828000009059906,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.0681999996304512,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/header","display_name":"Header","score":0.7556999921798706},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.661300003528595},{"id":"https://openalex.org/keywords/initialization","display_name":"Initialization","score":0.5583000183105469},{"id":"https://openalex.org/keywords/cyclic-redundancy-check","display_name":"Cyclic redundancy check","score":0.5494999885559082},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5041000247001648},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.4643000066280365},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.45419999957084656},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.44339999556541443},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4433000087738037}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7736999988555908},{"id":"https://openalex.org/C48105269","wikidata":"https://www.wikidata.org/wiki/Q1141160","display_name":"Header","level":2,"score":0.7556999921798706},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.661300003528595},{"id":"https://openalex.org/C114466953","wikidata":"https://www.wikidata.org/wiki/Q6034165","display_name":"Initialization","level":2,"score":0.5583000183105469},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5523999929428101},{"id":"https://openalex.org/C137627569","wikidata":"https://www.wikidata.org/wiki/Q245471","display_name":"Cyclic redundancy check","level":3,"score":0.5494999885559082},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5041000247001648},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.4643000066280365},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.45419999957084656},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.44339999556541443},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4433000087738037},{"id":"https://openalex.org/C185588885","wikidata":"https://www.wikidata.org/wiki/Q7553811","display_name":"Soft-decision decoder","level":3,"score":0.43779999017715454},{"id":"https://openalex.org/C117379686","wikidata":"https://www.wikidata.org/wiki/Q6996459","display_name":"Viterbi decoder","level":3,"score":0.42750000953674316},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.38350000977516174},{"id":"https://openalex.org/C2780505938","wikidata":"https://www.wikidata.org/wiki/Q17093282","display_name":"Unavailability","level":2,"score":0.36890000104904175},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.367000013589859},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36419999599456787},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3531999886035919},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.33239999413490295},{"id":"https://openalex.org/C2778571676","wikidata":"https://www.wikidata.org/wiki/Q3317826","display_name":"ModelSim","level":4,"score":0.3264999985694885},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.31929999589920044},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3172000050544739},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.3061999976634979},{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.26589998602867126},{"id":"https://openalex.org/C116834253","wikidata":"https://www.wikidata.org/wiki/Q2039217","display_name":"Identification (biology)","level":2,"score":0.26510000228881836},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.25839999318122864},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2583000063896179}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2026.3662461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2026.3662461","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7945128679275513,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G2351528596","display_name":null,"funder_award_id":"62227816","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7121654242","display_name":null,"funder_award_id":"62434007","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G7321967598","display_name":null,"funder_award_id":"252300421800","funder_id":"https://openalex.org/F4320323845","funder_display_name":"Natural Science Foundation of Henan Province"},{"id":"https://openalex.org/G7691965228","display_name":null,"funder_award_id":"242300421704","funder_id":"https://openalex.org/F4320323845","funder_display_name":"Natural Science Foundation of Henan Province"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320323845","display_name":"Natural Science Foundation of Henan Province","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0],"JESD204C":[1,44,178],"receiver":[2,179],"has":[3],"emerged":[4],"as":[5,20],"a":[6,47,73,126,133,154,183],"mainstream":[7],"SerDes":[8],"interface":[9],"in":[10,140],"high-speed":[11],"analog-to-digital":[12],"converters":[13],"(ADCs).":[14],"However,":[15],"it":[16],"faces":[17],"challenges":[18],"such":[19],"long":[21],"link":[22,110,122,208],"initialization":[23],"time,":[24],"substantial":[25],"hardware":[26,151,213,221],"area":[27,59,117,222],"and":[28,56,65,103,128,146,187,206,223,230],"power":[29,224],"consumption.":[30],"To":[31],"address":[32],"these":[33],"issues,":[34],"this":[35,86],"paper":[36],"presents":[37],"an":[38,190],"optimized":[39],"link-layer":[40],"design":[41,198],"for":[42],"the":[43,58,93,100,106,115,120,141,167,176,197,220,234],"receiver,":[45],"with":[46,132,182,217],"focus":[48],"on":[49,189],"enhancing":[50],"synchronization":[51,107],"header":[52],"(SH)":[53],"detection":[54,78,204],"efficiency":[55],"reducing":[57,149],"of":[60,99,119],"Cyclic":[61],"Redundancy":[62],"Check":[63],"(CRC)":[64],"Forward":[66],"Error":[67],"Correction":[68],"(FEC)":[69],"decoding":[70,124,142],"circuits.":[71],"First,":[72],"dynamic":[74],"search":[75],"space(DSS)-based":[76],"SH":[77,102,203,235],"method":[79,87],"is":[80,136,160,180,238],"proposed.":[81],"Leveraging":[82],"multi-level":[83],"XOR":[84],"logic,":[85],"efficiently":[88],"eliminates":[89,201],"non-transition":[90],"bits":[91],"from":[92],"data":[94,121],"stream,":[95],"enabling":[96],"rapid":[97],"localization":[98],"2-bit":[101],"thus":[104],"shortening":[105],"delay":[108],"during":[109],"establishment.":[111],"Second,":[112],"to":[113,162],"mitigate":[114],"large":[116],"overhead":[118],"layers":[123],"module,":[125],"CRC":[127],"FEC":[129],"decoder":[130,168],"(CAFD)":[131],"logic-sharing":[134],"architecture":[135],"designed:":[137],"common":[138],"factors":[139],"process":[143,186],"are":[144,226],"identified":[145],"shared,":[147],"significantly":[148],"redundant":[150,202],"resources.":[152],"Additionally,":[153],"low-complexity":[155],"critical":[156],"path":[157],"identification":[158],"algorithm":[159],"introduced":[161],"guide":[163],"factor-sharing":[164],"constraints,":[165],"ensuring":[166],"meets":[169],"timing":[170],"requirements":[171],"while":[172,233],"optimizing":[173],"area.":[174],"Finally,":[175],"proposed":[177],"implemented":[181],"28-nm":[184],"CMOS":[185],"verified":[188],"FPGA":[191],"platform.":[192],"Experimental":[193],"results":[194],"show":[195],"that":[196],"not":[199],"only":[200],"operations":[205],"accelerates":[207],"initialization/synchronization":[209],"but":[210],"also":[211],"improves":[212],"resource":[214],"utilization.":[215],"Compared":[216],"state-of-the-art":[218],"solutions,":[219],"consumption":[225],"reduced":[227],"by":[228,240],"47.6%":[229],"15.1%,":[231],"respectively,":[232],"locking":[236],"time":[237],"shortened":[239],"60%.":[241]},"counts_by_year":[],"updated_date":"2026-07-01T06:00:48.157686","created_date":"2026-02-27T00:00:00"}
