{"id":"https://openalex.org/W4417438484","doi":"https://doi.org/10.1109/tcsi.2025.3641690","title":"Robust Convergence in a Class of Nonlinear Circuits With Memristors","display_name":"Robust Convergence in a Class of Nonlinear Circuits With Memristors","publication_year":2025,"publication_date":"2025-12-17","ids":{"openalex":"https://openalex.org/W4417438484","doi":"https://doi.org/10.1109/tcsi.2025.3641690"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3641690","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3641690","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080374992","display_name":"Mauro Di Marco","orcid":"https://orcid.org/0000-0002-0013-9112"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Di Marco","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"raw_orcid":"https://orcid.org/0000-0002-0013-9112","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069809502","display_name":"Mauro Forti","orcid":"https://orcid.org/0000-0002-3970-7201"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Forti","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"raw_orcid":"https://orcid.org/0000-0002-3970-7201","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003092391","display_name":"Luca Pancioni","orcid":"https://orcid.org/0000-0002-2502-9542"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Pancioni","raw_affiliation_strings":["Department of Information Engineering and Mathematics, University of Siena, Siena, Italy"],"raw_orcid":"https://orcid.org/0000-0002-2502-9542","affiliations":[{"raw_affiliation_string":"Department of Information Engineering and Mathematics, University of Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078497169","display_name":"Giacomo Innocenti","orcid":"https://orcid.org/0000-0002-2110-826X"},"institutions":[{"id":"https://openalex.org/I45084792","display_name":"University of Florence","ror":"https://ror.org/04jr1s763","country_code":"IT","type":"education","lineage":["https://openalex.org/I45084792"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giacomo Innocenti","raw_affiliation_strings":["Department of Information Engineering, University of Florence, Firenze, Italy"],"raw_orcid":"https://orcid.org/0000-0002-2110-826X","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Florence, Firenze, Italy","institution_ids":["https://openalex.org/I45084792"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074942219","display_name":"A. Tesi","orcid":"https://orcid.org/0000-0002-0234-5999"},"institutions":[{"id":"https://openalex.org/I45084792","display_name":"University of Florence","ror":"https://ror.org/04jr1s763","country_code":"IT","type":"education","lineage":["https://openalex.org/I45084792"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Tesi","raw_affiliation_strings":["Department of Information Engineering, University of Florence, Firenze, Italy"],"raw_orcid":"https://orcid.org/0000-0002-0234-5999","affiliations":[{"raw_affiliation_string":"Department of Information Engineering, University of Florence, Firenze, Italy","institution_ids":["https://openalex.org/I45084792"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.34254322,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"73","issue":"6","first_page":"4308","last_page":"4321"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9157999753952026,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9157999753952026,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11347","display_name":"Neural Networks Stability and Synchronization","score":0.04019999876618385,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.01720000058412552,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.7901999950408936},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.7488999962806702},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.6973999738693237},{"id":"https://openalex.org/keywords/convergence","display_name":"Convergence (economics)","score":0.694100022315979},{"id":"https://openalex.org/keywords/resistor","display_name":"Resistor","score":0.5703999996185303},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.412200003862381},{"id":"https://openalex.org/keywords/reciprocity","display_name":"Reciprocity (cultural anthropology)","score":0.38929998874664307},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3880000114440918}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.7901999950408936},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.7488999962806702},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.6973999738693237},{"id":"https://openalex.org/C2777303404","wikidata":"https://www.wikidata.org/wiki/Q759757","display_name":"Convergence (economics)","level":2,"score":0.694100022315979},{"id":"https://openalex.org/C137488568","wikidata":"https://www.wikidata.org/wiki/Q5321","display_name":"Resistor","level":3,"score":0.5703999996185303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44909998774528503},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.412200003862381},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4052000045776367},{"id":"https://openalex.org/C169903001","wikidata":"https://www.wikidata.org/wiki/Q3264987","display_name":"Reciprocity (cultural anthropology)","level":2,"score":0.38929998874664307},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3880000114440918},{"id":"https://openalex.org/C196796808","wikidata":"https://www.wikidata.org/wiki/Q132629","display_name":"Electrical network","level":2,"score":0.36419999599456787},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3598000109195709},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.35679998993873596},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34950000047683716},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.34209999442100525},{"id":"https://openalex.org/C5871375","wikidata":"https://www.wikidata.org/wiki/Q1780715","display_name":"Compact convergence","level":4,"score":0.30799999833106995},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.3037000000476837},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2874000072479248},{"id":"https://openalex.org/C117898588","wikidata":"https://www.wikidata.org/wiki/Q6664310","display_name":"Local convergence","level":3,"score":0.28619998693466187},{"id":"https://openalex.org/C94766913","wikidata":"https://www.wikidata.org/wiki/Q1530271","display_name":"Equilibrium point","level":3,"score":0.2676999866962433},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.2538999915122986}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcsi.2025.3641690","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3641690","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:flore.unifi.it:2158/1450564","is_oa":false,"landing_page_url":"https://hdl.handle.net/2158/1450564","pdf_url":null,"source":{"id":"https://openalex.org/S4306402033","display_name":"Florence Research (University of Florence)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45084792","host_organization_name":"University of Florence","host_organization_lineage":["https://openalex.org/I45084792"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/1306721","is_oa":false,"landing_page_url":"https://hdl.handle.net/11365/1306721","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Convergence":[0,65],"of":[1,10,91,95,107,138,160,174,193],"nonlinear":[2,28,108],"circuits":[3,29,85,109,131],"towards":[4],"equilibrium":[5],"points":[6],"(EPs)":[7],"is":[8,24,41,97,120,191],"one":[9],"the":[11,71,77,89,146,157,175,194],"most":[12],"basic":[13,139],"properties":[14],"both":[15],"from":[16],"a":[17,20,34,105,152],"theoretic":[18],"and":[19,117,151,178],"practical":[21],"viewpoint.":[22],"It":[23],"especially":[25],"relevant":[26],"for":[27,156,164,172],"modeling":[30],"neural":[31],"networks,":[32],"since":[33,126],"convergent":[35],"network":[36],"with":[37,132],"multiple":[38,51,133],"stable":[39,54,134],"EPs":[40,55],"tailor":[42],"made":[43,192],"to":[44,57,84,129],"implement":[45],"content":[46],"addressable":[47],"memories":[48],"(CAMs)":[49],"storing":[50],"patterns":[52],"as":[53],"or":[56,114],"solve":[58],"combinatorial":[59],"optimization":[60],"problems":[61],"in":[62,70,93,99],"real":[63],"time.":[64],"has":[66],"been":[67],"widely":[68],"investigated":[69],"last":[72],"few":[73],"decades.":[74],"By":[75],"far,":[76],"available":[78],"convergence":[79,92,142,165],"results":[80,140,183],"can":[81],"be":[82],"applied":[83],"without":[86],"memristors,":[87,111],"while":[88],"study":[90],"presence":[94],"memristors":[96],"only":[98],"its":[100],"infancy.":[101],"In":[102],"this":[103],"paper,":[104],"class":[106,159],"containing":[110],"capacitors,":[112],"passive":[113],"active":[115],"resistors":[116,123],"independent":[118],"sources,":[119],"considered.":[121],"Active":[122],"are":[124,143,166,184],"crucial,":[125],"they":[127,169],"permit":[128],"obtain":[130],"EPs.":[135],"A":[136],"number":[137],"on":[141],"obtained":[144],"via":[145,186],"flux-charge":[147],"analysis":[148],"method":[149],"(FCAM)":[150],"fundamental":[153],"reciprocity":[154],"principle":[155],"considered":[158],"circuits.":[161],"The":[162,182],"conditions":[163],"robust,":[167],"i.e.,":[168],"hold":[170],"also":[171],"perturbations":[173],"circuit":[176],"parameters":[177],"memristor":[179,197],"nonlinearities":[180],"involved.":[181],"illustrated":[185],"selected":[187],"examples":[188],"where":[189],"use":[190],"celebrated":[195],"HP":[196],"model.":[198]},"counts_by_year":[],"updated_date":"2026-06-02T06:17:35.589633","created_date":"2025-12-17T00:00:00"}