{"id":"https://openalex.org/W4415707030","doi":"https://doi.org/10.1109/tcsi.2025.3625509","title":"An Efficient Approximate Radix-8 Booth Multiplier for Edge Detection in Bioimages by Field Programmable Gate Array","display_name":"An Efficient Approximate Radix-8 Booth Multiplier for Edge Detection in Bioimages by Field Programmable Gate Array","publication_year":2025,"publication_date":"2025-10-30","ids":{"openalex":"https://openalex.org/W4415707030","doi":"https://doi.org/10.1109/tcsi.2025.3625509"},"language":null,"primary_location":{"id":"doi:10.1109/tcsi.2025.3625509","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3625509","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5120192571","display_name":"Elham Esmaeili","orcid":"https://orcid.org/0000-0002-5484-5899"},"institutions":[{"id":"https://openalex.org/I91138267","display_name":"Islamic Azad University of Shiraz","ror":"https://ror.org/03xbchh53","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I91138267"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Elham Esmaeili","raw_affiliation_strings":["Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran"],"raw_orcid":"https://orcid.org/0000-0002-5484-5899","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran","institution_ids":["https://openalex.org/I91138267"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114090431","display_name":"A.M. Ranjbar","orcid":null},"institutions":[{"id":"https://openalex.org/I91138267","display_name":"Islamic Azad University of Shiraz","ror":"https://ror.org/03xbchh53","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I91138267"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Ali Ranjbar","raw_affiliation_strings":["Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran"],"raw_orcid":"https://orcid.org/0009-0006-0691-9044","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran","institution_ids":["https://openalex.org/I91138267"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5120192572","display_name":"Shabnam Rafiei","orcid":null},"institutions":[{"id":"https://openalex.org/I91138267","display_name":"Islamic Azad University of Shiraz","ror":"https://ror.org/03xbchh53","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I91138267"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Shabnam Rafiei","raw_affiliation_strings":["Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran"],"raw_orcid":"https://orcid.org/0000-0003-0298-1167","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran","institution_ids":["https://openalex.org/I91138267"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019926942","display_name":"Nabiollah Shiri","orcid":"https://orcid.org/0000-0003-4683-1814"},"institutions":[{"id":"https://openalex.org/I91138267","display_name":"Islamic Azad University of Shiraz","ror":"https://ror.org/03xbchh53","country_code":"IR","type":"education","lineage":["https://openalex.org/I110525433","https://openalex.org/I91138267"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Nabiollah Shiri","raw_affiliation_strings":["Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran"],"raw_orcid":"https://orcid.org/0000-0003-4683-1814","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Shi.C.,, Islamic Azad University, Shiraz, Iran","institution_ids":["https://openalex.org/I91138267"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I91138267"],"apc_list":null,"apc_paid":null,"fwci":0.5057,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.71210962,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":"73","issue":"3","first_page":"1924","last_page":"1933"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7480000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.7480000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.10790000110864639,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.055399999022483826,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sobel-operator","display_name":"Sobel operator","score":0.7820000052452087},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7249000072479248},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.583299994468689},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5803999900817871},{"id":"https://openalex.org/keywords/booths-multiplication-algorithm","display_name":"Booth's multiplication algorithm","score":0.5799999833106995},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5763000249862671},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5221999883651733},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4124000072479248},{"id":"https://openalex.org/keywords/row","display_name":"Row","score":0.4066999852657318},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.4032999873161316}],"concepts":[{"id":"https://openalex.org/C30703548","wikidata":"https://www.wikidata.org/wiki/Q1757673","display_name":"Sobel operator","level":5,"score":0.7820000052452087},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7249000072479248},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.583299994468689},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5803999900817871},{"id":"https://openalex.org/C72475854","wikidata":"https://www.wikidata.org/wiki/Q477049","display_name":"Booth's multiplication algorithm","level":4,"score":0.5799999833106995},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5763000249862671},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5221999883651733},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4657999873161316},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.41260001063346863},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4124000072479248},{"id":"https://openalex.org/C135598885","wikidata":"https://www.wikidata.org/wiki/Q1366302","display_name":"Row","level":2,"score":0.4066999852657318},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.4032999873161316},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.39719998836517334},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.38609999418258667},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.38029998540878296},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3353999853134155},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.33500000834465027},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3328999876976013},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.3314000070095062},{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.3149999976158142},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31310001015663147},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.30889999866485596},{"id":"https://openalex.org/C193536780","wikidata":"https://www.wikidata.org/wiki/Q1513153","display_name":"Edge detection","level":4,"score":0.30390000343322754},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.296099990606308},{"id":"https://openalex.org/C2777892113","wikidata":"https://www.wikidata.org/wiki/Q5527005","display_name":"Gate count","level":2,"score":0.29600000381469727},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.28870001435279846},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.28029999136924744},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.2721000015735626},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.2612000107765198},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.25999999046325684},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.2596000134944916},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.2572000026702881},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25619998574256897},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.2547999918460846}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3625509","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3625509","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0,96,132,151,186],"Booth":[1,18,99],"multiplier":[2,133,174],"provides":[3],"high-performance":[4],"signed":[5,110],"multiplication":[6],"by":[7,80],"encoding":[8],"and":[9,29,53,83,101,120,157,210,217],"decreasing":[10],"partial":[11],"products":[12],"(PPs)":[13],"generated":[14,48],"using":[15,65],"the":[16,21,27,41,45,76,81,87,93,145,172,178,193,204],"radix-4":[17,28],"algorithm.":[19],"Although":[20],"radix-8":[22,98],"produces":[23],"fewer":[24,31],"PPs":[25],"than":[26],"needs":[30],"adders":[32],"to":[33,107,143,177],"accumulate":[34],"PPs,":[35],"it":[36],"is":[37,58,72,134],"not":[38],"fast":[39],"because":[40],"odd":[42],"multiples":[43],"of":[44,89,171,183,197],"multiplicand":[46],"are":[47,78,105,175,215],"in":[49,74,92],"a":[50,55,109,123],"complex":[51],"unit,":[52],"attaining":[54],"high":[56],"performance":[57],"challenging.":[59],"This":[60],"work":[61],"alleviates":[62],"this":[63],"issue":[64],"approximate":[66,69,118],"designs.":[67],"An":[68],"4:2":[70],"compressor":[71],"proposed":[73],"which":[75],"inputs":[77],"encoded":[79],"generation":[82,103],"propagation":[84],"method":[85],"for":[86,148],"reduction":[88],"faulty":[90],"rows":[91],"truth":[94],"table.":[95],"compressor,":[97],"encoder,":[100],"PP":[102],"(PPG)":[104],"used":[106],"attain":[108],"<inline-formula":[111],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[112,160],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[113,161],"<tex-math":[114,162],"notation=\"LaTeX\">$16\\times":[115],"16$</tex-math>":[116],"</inline-formula>-bit,":[117],"multiplier,":[119],"synthesized":[121],"targeting":[122],"90":[124],"nm":[125],"complementary":[126],"metal":[127],"oxide":[128],"semiconductor":[129],"(CMOS)":[130],"technology.":[131],"efficiently":[135],"implemented":[136,191],"on":[137,192],"field":[138],"programmable":[139],"gate":[140],"arrays":[141],"(FPGAs)":[142],"perform":[144],"Sobel":[146,187],"operator":[147],"edge":[149,188],"detection.":[150],"occupied":[152],"area,":[153],"dynamic":[154],"power":[155],"dissipation,":[156],"power-delay-product":[158],"(PDP)<inline-formula":[159],"notation=\"LaTeX\">$\\times":[163],"$</tex-math>":[164],"</inline-formula>":[165],"mean":[166],"relative":[167],"error":[168],"distance":[169],"(MRED)":[170],"presented":[173],"superior":[176],"lookup":[179],"table":[180],"(LUT)-based":[181],"multipliers":[182],"an":[184],"FPGA.":[185],"detection":[189],"algorithm":[190],"FPGA":[194],"detects":[195],"99.15%":[196],"edges":[198],"with":[199],"33.33%":[200],"energy":[201],"savings,":[202],"while":[203],"structural":[205],"similarity":[206],"index":[207],"measure":[208],"(SSIM)":[209],"peak":[211],"signal-to-noise":[212],"ratio":[213],"(PSNR)":[214],"0.88":[216],"32.92dB,":[218],"respectively.":[219]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-30T00:00:00"}