{"id":"https://openalex.org/W7101713462","doi":"https://doi.org/10.1109/tcsi.2025.3623568","title":"Analysis and Design of Multitasking Memristor Cellular Nonlinear Networks","display_name":"Analysis and Design of Multitasking Memristor Cellular Nonlinear Networks","publication_year":2025,"publication_date":"2025-10-28","ids":{"openalex":"https://openalex.org/W7101713462","doi":"https://doi.org/10.1109/tcsi.2025.3623568"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3623568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3623568","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://vbn.aau.dk/da/publications/1bdf4932-f87d-4871-ad6e-ba049ba8f02f","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Vasileios Ntinas","orcid":"https://orcid.org/0000-0002-2367-5567"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Vasileios Ntinas","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-2367-5567","affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Dimitrios Prousalis","orcid":"https://orcid.org/0000-0002-6200-4707"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Dimitrios Prousalis","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-6200-4707","affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Yongmin Wang","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yongmin Wang","raw_affiliation_strings":["Peter Grünberg Institut (PGI-10), Forschungszentrum Jülich GmbH, Jülich, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peter Grünberg Institut (PGI-10), Forschungszentrum Jülich GmbH, Jülich, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ahmet Samil Demirkol","orcid":"https://orcid.org/0000-0002-1236-1300"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ahmet Samil Demirkol","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-1236-1300","affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Ioannis Messaris","orcid":"https://orcid.org/0000-0002-4286-6553"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ioannis Messaris","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0002-4286-6553","affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Vikas Rana","orcid":"https://orcid.org/0000-0001-5432-0286"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Vikas Rana","raw_affiliation_strings":["Peter Grünberg Institut (PGI-10), Forschungszentrum Jülich GmbH, Jülich, Germany"],"raw_orcid":"https://orcid.org/0000-0001-5432-0286","affiliations":[{"raw_affiliation_string":"Peter Grünberg Institut (PGI-10), Forschungszentrum Jülich GmbH, Jülich, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Stephan Menzel","orcid":"https://orcid.org/0000-0002-4258-2673"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Stephan Menzel","raw_affiliation_strings":["Peter Grünberg Institut (PGI-7), Forschungszentrum Jülich GmbH, Jülich, Germany"],"raw_orcid":"https://orcid.org/0000-0002-4258-2673","affiliations":[{"raw_affiliation_string":"Peter Grünberg Institut (PGI-7), Forschungszentrum Jülich GmbH, Jülich, Germany","institution_ids":[]}]},{"author_position":"middle","author":{"id":null,"display_name":"Alon Ascoli","orcid":"https://orcid.org/0000-0003-4026-9648"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Politecnico di Torino","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alon Ascoli","raw_affiliation_strings":["Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy"],"raw_orcid":"https://orcid.org/0000-0003-4026-9648","affiliations":[{"raw_affiliation_string":"Department of Electronics and Telecommunications, Politecnico di Torino, Turin, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":null,"display_name":"Ronald Tetzlaff","orcid":"https://orcid.org/0000-0001-7436-0103"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ronald Tetzlaff","raw_affiliation_strings":["Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany"],"raw_orcid":"https://orcid.org/0000-0001-7436-0103","affiliations":[{"raw_affiliation_string":"Faculty of Electrical and Computer Engineering, Institute of Circuits and Systems, TUD | Dresden University of Technology, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.8287,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.93833068,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"73","issue":"4","first_page":"2438","last_page":"2451"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T12568","display_name":"Plant Taxonomy and Phylogenetics","score":0.10170000046491623,"subfield":{"id":"https://openalex.org/subfields/1105","display_name":"Ecology, Evolution, Behavior and Systematics"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T12568","display_name":"Plant Taxonomy and Phylogenetics","score":0.10170000046491623,"subfield":{"id":"https://openalex.org/subfields/1105","display_name":"Ecology, Evolution, Behavior and Systematics"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T11927","display_name":"Plant Reproductive Biology","score":0.08389999717473984,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T10434","display_name":"Chromosomal and Genetic Variations","score":0.06769999861717224,"subfield":{"id":"https://openalex.org/subfields/1110","display_name":"Plant Science"},"field":{"id":"https://openalex.org/fields/11","display_name":"Agricultural and Biological Sciences"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/human-multitasking","display_name":"Human multitasking","score":0.9223999977111816},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.6959999799728394},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.5932999849319458},{"id":"https://openalex.org/keywords/task","display_name":"Task (project management)","score":0.44920000433921814},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.349700003862381},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.33980000019073486}],"concepts":[{"id":"https://openalex.org/C107418235","wikidata":"https://www.wikidata.org/wiki/Q1520565","display_name":"Human multitasking","level":2,"score":0.9223999977111816},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.705299973487854},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.6959999799728394},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.5932999849319458},{"id":"https://openalex.org/C2780451532","wikidata":"https://www.wikidata.org/wiki/Q759676","display_name":"Task (project management)","level":2,"score":0.44920000433921814},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3709000051021576},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.349700003862381},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.33980000019073486},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.32010000944137573},{"id":"https://openalex.org/C79379906","wikidata":"https://www.wikidata.org/wiki/Q3174497","display_name":"Dynamical systems theory","level":2,"score":0.32010000944137573},{"id":"https://openalex.org/C36464697","wikidata":"https://www.wikidata.org/wiki/Q451553","display_name":"Visualization","level":2,"score":0.30809998512268066},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.29319998621940613},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.2879999876022339},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.28679999709129333},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2752000093460083},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.27410000562667847},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.27309998869895935},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.26899999380111694},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.2648000121116638}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/tcsi.2025.3623568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3623568","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:juser.fz-juelich.de:1048179","is_oa":false,"landing_page_url":"https://juser.fz-juelich.de/record/1048179","pdf_url":null,"source":{"id":"https://openalex.org/S4306401090","display_name":"JuSER (Forschungszentrum J\u00fclich)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I171892758","host_organization_name":"Forschungszentrum J\u00fclich","host_organization_lineage":["https://openalex.org/I171892758"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE transactions on circuits and systems / 1 1, 1 - 14 (2025). doi:10.1109/TCSI.2025.3623568","raw_type":"info:eu-repo/semantics/article"},{"id":"pmh:oai:pure.atira.dk:openaire/1bdf4932-f87d-4871-ad6e-ba049ba8f02f","is_oa":true,"landing_page_url":"https://vbn.aau.dk/da/publications/1bdf4932-f87d-4871-ad6e-ba049ba8f02f","pdf_url":null,"source":{"id":"https://openalex.org/S4306401731","display_name":"VBN Forskningsportal (Aalborg Universitet)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I891191580","host_organization_name":"Aalborg University","host_organization_lineage":["https://openalex.org/I891191580"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ntinas, V, Prousalis, D, Wang, Y, Demirkol, A S, Messaris, I, Rana, V, Menzel, S, Ascoli, A & Tetzlaff, R 2026, 'Analysis and Design of Multitasking Memristor Cellular Nonlinear Networks', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 4, pp. 2438-2451. https://doi.org/10.1109/TCSI.2025.3623568","raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":{"id":"pmh:oai:pure.atira.dk:openaire/1bdf4932-f87d-4871-ad6e-ba049ba8f02f","is_oa":true,"landing_page_url":"https://vbn.aau.dk/da/publications/1bdf4932-f87d-4871-ad6e-ba049ba8f02f","pdf_url":null,"source":{"id":"https://openalex.org/S4306401731","display_name":"VBN Forskningsportal (Aalborg Universitet)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I891191580","host_organization_name":"Aalborg University","host_organization_lineage":["https://openalex.org/I891191580"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Ntinas, V, Prousalis, D, Wang, Y, Demirkol, A S, Messaris, I, Rana, V, Menzel, S, Ascoli, A & Tetzlaff, R 2026, 'Analysis and Design of Multitasking Memristor Cellular Nonlinear Networks', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 4, pp. 2438-2451. https://doi.org/10.1109/TCSI.2025.3623568","raw_type":"info:eu-repo/semantics/article"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.7828586101531982}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"Cellular":[0,67,131],"Nonlinear":[1,68,132],"Networks":[2,69,133],"(CellNNs)":[3],"represent":[4],"a":[5,53,58,111,117,170,187],"promising":[6],"computational":[7],"paradigm,":[8],"renowned":[9],"for":[10,61,181,195],"their":[11,34],"massively":[12],"parallel":[13],"operation":[14,64],"and":[15,17,57,95,125,157,197,231,237],"energy-efficient,":[16],"real-time":[18],"multi-dimensional":[19],"signal":[20],"processing":[21],"capabilities.":[22],"The":[23],"recent":[24],"incorporation":[25],"of":[26,74,80,92,128,160,208,239],"memristors":[27],"into":[28,223],"CellNN":[29],"architectures":[30],"has":[31],"notably":[32],"enhanced":[33,217],"functionality":[35,198],"by":[36,102,147,212],"introducing":[37],"analog,":[38],"non-volatile":[39],"memory":[40],"elements":[41],"that":[42,120],"enrich":[43],"the":[44,78,89,96,103,122,138,155,177,205,213,234],"networks\u2019":[45],"dynamic":[46],"behavior.":[47],"In":[48,106],"this":[49,75,107],"paper,":[50,108],"we":[51,109,136,168,200],"present":[52],"rigorous":[54,112],"dynamical":[55,113],"analysis":[56,114],"structured":[59,118],"methodology":[60,119,203],"designing":[62],"multitasking":[63,129,184,209,240],"in":[65],"Memristor":[66,130],"(M-CellNNs).":[70,134],"A":[71],"distinctive":[72],"outcome":[73],"enhancement":[76],"is":[77,99],"possibility":[79],"multitasking,":[81],"where":[82],"different":[83],"operations":[84],"can":[85],"be":[86],"performed":[87],"with":[88,116],"same":[90],"set":[91],"design":[93,124,193],"parameters,":[94],"executed":[97],"task":[98],"determined":[100],"solely":[101],"memristor\u2019s":[104],"state.":[105],"develop":[110],"together":[115],"enable":[121],"systematic":[123,171],"reliable":[126,206],"implementation":[127],"Methodologically,":[135],"extend":[137],"second-order":[139],"Dynamic":[140],"Route":[141],"Map":[142],"(DRM2)":[145],"technique":[146],"integrating":[148],"vector-field-based":[149],"phase":[150],"plane":[151],"analysis,":[152],"significantly":[153,232],"improving":[154],"visualization":[156],"analytical":[158,172,218],"characterization":[159],"realistic":[161],"memristor":[162],"dynamics":[163],"within":[164],"M-CellNN":[165,191,241],"cells.":[166],"Additionally,":[167],"propose":[169],"framework":[173],"to":[174],"precisely":[175],"define":[176],"parameter":[178,229],"spaces":[179],"necessary":[180],"achieving":[182],"targeted":[183],"operations.":[185],"Using":[186],"practical":[188,235],"operational":[189],"amplifier-based":[190],"cell":[192],"well-suited":[194],"prototyping":[196],"testing,":[199],"demonstrate":[201],"our":[202],"through":[204],"execution":[207],"operations,":[210],"exemplified":[211],"CORNER-EDGE":[214],"task.":[215],"Our":[216],"tools":[219],"provide":[220],"intuitive":[221],"insights":[222],"complex":[224],"system":[225],"dynamics,":[226],"facilitating":[227],"accurate":[228],"selection":[230],"advancing":[233],"feasibility":[236],"reliability":[238],"implementations.":[242]},"counts_by_year":[{"year":2026,"cited_by_count":2}],"updated_date":"2026-03-31T06:02:25.137627","created_date":"2025-10-29T00:00:00"}