{"id":"https://openalex.org/W7101941710","doi":"https://doi.org/10.1109/tcsi.2025.3617327","title":"Characterizing the Intrinsic Bank-Level Accuracy Versus Energy Trade-Off of SRAM-Based Analog In-Memory Computing Architectures in 28 nm CMOS","display_name":"Characterizing the Intrinsic Bank-Level Accuracy Versus Energy Trade-Off of SRAM-Based Analog In-Memory Computing Architectures in 28 nm CMOS","publication_year":2025,"publication_date":"2025-10-28","ids":{"openalex":"https://openalex.org/W7101941710","doi":"https://doi.org/10.1109/tcsi.2025.3617327"},"language":null,"primary_location":{"id":"doi:10.1109/tcsi.2025.3617327","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3617327","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Shuo Li","orcid":"https://orcid.org/0000-0002-2024-2002"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Shuo Li","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Chihun Song","orcid":"https://orcid.org/0000-0001-9586-153X"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chihun Song","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hyungyo Kim","orcid":"https://orcid.org/0000-0002-1157-0127"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hyungyo Kim","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Nam Sung Kim","orcid":"https://orcid.org/0000-0002-0442-5634"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nam Sung Kim","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":null,"display_name":"Naresh R. Shanbhag","orcid":"https://orcid.org/0000-0002-4323-9164"},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Naresh R. Shanbhag","raw_affiliation_strings":["Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA"],"affiliations":[{"raw_affiliation_string":"Coordinated Science Laboratory, University of Illinois at Urbana–Champaign, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I157725225"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.50152542,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"73","issue":"2","first_page":"1010","last_page":"1023"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.4318000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.4318000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.299699991941452,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.09239999949932098,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.7080000042915344},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6851999759674072},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6816999912261963},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.5509999990463257},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.5170999765396118},{"id":"https://openalex.org/keywords/dimension","display_name":"Dimension (graph theory)","score":0.49959999322891235},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47909998893737793},{"id":"https://openalex.org/keywords/von-neumann-architecture","display_name":"Von Neumann architecture","score":0.47040000557899475}],"concepts":[{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.7080000042915344},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6851999759674072},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6816999912261963},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6534000039100647},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5813999772071838},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.5509999990463257},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.5170999765396118},{"id":"https://openalex.org/C33676613","wikidata":"https://www.wikidata.org/wiki/Q13415176","display_name":"Dimension (graph theory)","level":2,"score":0.49959999322891235},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47909998893737793},{"id":"https://openalex.org/C80469333","wikidata":"https://www.wikidata.org/wiki/Q189088","display_name":"Von Neumann architecture","level":2,"score":0.47040000557899475},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.4059999883174896},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.3977999985218048},{"id":"https://openalex.org/C2780009758","wikidata":"https://www.wikidata.org/wiki/Q6804172","display_name":"Measure (data warehouse)","level":2,"score":0.3790999948978424},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.32679998874664307},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29739999771118164},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.29269999265670776},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.28769999742507935},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.28049999475479126},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27799999713897705},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.27399998903274536},{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.27219998836517334},{"id":"https://openalex.org/C2776401178","wikidata":"https://www.wikidata.org/wiki/Q12050496","display_name":"Feature (linguistics)","level":2,"score":0.25049999356269836}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3617327","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3617327","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.9051550030708313,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":39,"referenced_works":["https://openalex.org/W1806144281","https://openalex.org/W1971325875","https://openalex.org/W2111186324","https://openalex.org/W2146276996","https://openalex.org/W2194775991","https://openalex.org/W2289252105","https://openalex.org/W2293829681","https://openalex.org/W2591601611","https://openalex.org/W2782511028","https://openalex.org/W2790511620","https://openalex.org/W2899641901","https://openalex.org/W2998765974","https://openalex.org/W2999356938","https://openalex.org/W3000296772","https://openalex.org/W3000301330","https://openalex.org/W3016014942","https://openalex.org/W3026786299","https://openalex.org/W3134526034","https://openalex.org/W3139521791","https://openalex.org/W3161810489","https://openalex.org/W3184281067","https://openalex.org/W3184748710","https://openalex.org/W3186879574","https://openalex.org/W3208788005","https://openalex.org/W3209059139","https://openalex.org/W4221038786","https://openalex.org/W4280533641","https://openalex.org/W4312949026","https://openalex.org/W4312951380","https://openalex.org/W4319996342","https://openalex.org/W4360605969","https://openalex.org/W4360606196","https://openalex.org/W4360606816","https://openalex.org/W4385245566","https://openalex.org/W4386764904","https://openalex.org/W4387129467","https://openalex.org/W4387411196","https://openalex.org/W4392746125","https://openalex.org/W4392746193"],"related_works":[],"abstract_inverted_index":{"In-memory":[0],"computing":[1,9],"(IMC)":[2],"architectures":[3,19,185],"are":[4,136],"emerging":[5],"as":[6,78],"the":[7,38,43,56,74,87,90,143,162,169,174,192],"next-generation":[8],"platforms":[10],"for":[11,98,108,149,157,182],"deep":[12],"learning":[13],"applications,":[14],"surpassing":[15],"traditional":[16],"von":[17],"Neumann":[18],"due":[20],"to":[21,85,109,198],"their":[22],"superior":[23],"energy":[24,47,134,180],"efficiency":[25],"and":[26,46,68,133,146,153,179,201],"computational":[27],"density.":[28],"However,":[29],"there":[30],"is":[31,121,168],"a":[32,61,79,96,105,158],"lack":[33],"of":[34,37,49,64,164,173,194],"comprehensive":[35],"understanding":[36,63],"trade-off":[39,175],"between":[40,176],"accuracy":[41,88,178],"at":[42,89],"bank":[44,91],"level":[45],"consumption":[48,135,181],"SRAM-based":[50,183],"IMCs,":[51],"which":[52],"execute":[53],"computations":[54],"in":[55,123],"analog":[57],"domain.":[58],"To":[59,161],"gain":[60],"complete":[62],"IMC\u2019s":[65],"fundamental":[66],"limits":[67],"design":[69],"space,":[70],"we":[71,94,103],"first":[72,170],"adopt":[73],"signal-to-noise-and-distortion":[75],"ratio":[76],"(SNDR)":[77],"metric,":[80],"inspired":[81],"by":[82],"ADC":[83],"design,":[84],"quantify":[86],"level.":[92],"Second,":[93],"propose":[95,104],"methodology":[97],"accurately":[99],"measuring":[100],"SNDR.":[101,113],"Finally,":[102],"chip":[106],"architecture":[107],"directly":[110],"measure":[111],"pre-ADC":[112],"This":[114],"characterization":[115],"chip,":[116],"incorporating":[117],"mainstream":[118],"IMC":[119,184,196,204],"architectures,":[120],"fabricated":[122],"28":[124],"nm":[125],"CMOS":[126],"technology.":[127],"Measurement":[128],"results":[129,190],"indicate":[130],"that":[131,138],"SNDR":[132,197],"trade-offs":[137],"can":[139],"be":[140],"adjusted":[141],"through":[142,154,186],"dot-product":[144],"dimension":[145],"wordline":[147],"voltage":[148,156],"charge/current":[150],"summing":[151],"models,":[152],"input-driver":[155],"charge-redistribution":[159],"model.":[160],"best":[163],"our":[165],"knowledge,":[166],"this":[167],"experimental":[171],"quantification":[172],"bank-level":[177],"silicon":[187],"measurements.":[188],"These":[189],"underscore":[191],"importance":[193],"characterizing":[195],"properly":[199],"benchmark":[200],"compare":[202],"future":[203],"designs.":[205]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-29T00:00:00"}