{"id":"https://openalex.org/W4414229164","doi":"https://doi.org/10.1109/tcsi.2025.3609463","title":"A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory","display_name":"A Complementary 3T-Based eDRAM Macro for High-Density Dual-Direction CAM and Logic-in-Memory","publication_year":2025,"publication_date":"2025-09-16","ids":{"openalex":"https://openalex.org/W4414229164","doi":"https://doi.org/10.1109/tcsi.2025.3609463"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3609463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3609463","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043838828","display_name":"Lintao Lan","orcid":null},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Lintao Lan","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5099841509","display_name":"Yuxin Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuxin Zhou","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115695295","display_name":"Jincheng Wang","orcid":"https://orcid.org/0009-0007-2826-6555"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jincheng Wang","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052045408","display_name":"Yifei Li","orcid":"https://orcid.org/0000-0002-3717-5432"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yifei Li","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Bin Ning","orcid":"https://orcid.org/0009-0003-4381-7109"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Bin Ning","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012064996","display_name":"Yuhao Shu","orcid":"https://orcid.org/0000-0002-0357-4507"},"institutions":[{"id":"https://openalex.org/I9842412","display_name":"Nanjing University of Aeronautics and Astronautics","ror":"https://ror.org/01scyh794","country_code":"CN","type":"education","lineage":["https://openalex.org/I9842412"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuhao Shu","raw_affiliation_strings":["College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, Nanjing, China"],"affiliations":[{"raw_affiliation_string":"College of Integrated Circuits, Nanjing University of Aeronautics and Astronautics, Nanjing, China","institution_ids":["https://openalex.org/I9842412"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008696855","display_name":"Hui Wang","orcid":"https://orcid.org/0000-0003-3897-3767"},"institutions":[{"id":"https://openalex.org/I4210111959","display_name":"Shanghai Advanced Research Institute","ror":"https://ror.org/02br7py06","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210111959"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hui Wang","raw_affiliation_strings":["School of Microelectronics, Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, Shanghai Advanced Research Institute, Chinese Academy of Sciences, Shanghai, China","institution_ids":["https://openalex.org/I4210111959"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084305618","display_name":"Yajun Ha","orcid":"https://orcid.org/0000-0003-4244-5916"},"institutions":[{"id":"https://openalex.org/I30809798","display_name":"ShanghaiTech University","ror":"https://ror.org/030bhh786","country_code":"CN","type":"education","lineage":["https://openalex.org/I30809798"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yajun Ha","raw_affiliation_strings":["School of Information Science and Technology, ShanghaiTech University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"School of Information Science and Technology, ShanghaiTech University, Shanghai, China","institution_ids":["https://openalex.org/I30809798"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5043838828"],"corresponding_institution_ids":["https://openalex.org/I30809798"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.23576684,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"73","issue":"2","first_page":"1024","last_page":"1037"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.7501999735832214},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5217000246047974},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5171999931335449},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.46939998865127563},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.453000009059906},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4490000009536743},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4406999945640564},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.4359999895095825},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4092999994754791},{"id":"https://openalex.org/keywords/random-access","display_name":"Random access","score":0.39739999175071716}],"concepts":[{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.7501999735832214},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6492000222206116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5727999806404114},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5217000246047974},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5171999931335449},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47099998593330383},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.46939998865127563},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.453000009059906},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4490000009536743},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4406999945640564},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.4359999895095825},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4092999994754791},{"id":"https://openalex.org/C101722063","wikidata":"https://www.wikidata.org/wiki/Q218825","display_name":"Random access","level":2,"score":0.39739999175071716},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38940000534057617},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.35280001163482666},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.34139999747276306},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.3343999981880188},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3264000117778778},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.32440000772476196},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.32350000739097595},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.3125999867916107},{"id":"https://openalex.org/C10418432","wikidata":"https://www.wikidata.org/wiki/Q560370","display_name":"AND gate","level":3,"score":0.303600013256073},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.29660001397132874},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.2955000102519989},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2874999940395355},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.2865000069141388},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.2827000021934509},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.2824999988079071},{"id":"https://openalex.org/C2776321774","wikidata":"https://www.wikidata.org/wiki/Q891131","display_name":"Read-write memory","level":3,"score":0.2808000147342682},{"id":"https://openalex.org/C2780866740","wikidata":"https://www.wikidata.org/wiki/Q5227345","display_name":"Data retention","level":2,"score":0.27790001034736633},{"id":"https://openalex.org/C89836824","wikidata":"https://www.wikidata.org/wiki/Q160710","display_name":"Read-only memory","level":2,"score":0.2678000032901764},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.2662000060081482},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.26570001244544983},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.2630000114440918},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.26260000467300415},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.25920000672340393},{"id":"https://openalex.org/C28495749","wikidata":"https://www.wikidata.org/wiki/Q155516","display_name":"XOR gate","level":3,"score":0.2500999867916107}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3609463","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3609463","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1314806456","display_name":null,"funder_award_id":"U2441247","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G1385045742","display_name":null,"funder_award_id":"62220106011","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1619268095","https://openalex.org/W1806144281","https://openalex.org/W1827639723","https://openalex.org/W1968310982","https://openalex.org/W1971936677","https://openalex.org/W2062143991","https://openalex.org/W2095425517","https://openalex.org/W2103664004","https://openalex.org/W2161091390","https://openalex.org/W2319489345","https://openalex.org/W2331783522","https://openalex.org/W2510570314","https://openalex.org/W2754347129","https://openalex.org/W2771238178","https://openalex.org/W2800944932","https://openalex.org/W2899053578","https://openalex.org/W2906571642","https://openalex.org/W3005980996","https://openalex.org/W3015947796","https://openalex.org/W3126970610","https://openalex.org/W3134925155","https://openalex.org/W3157529438","https://openalex.org/W4225350157","https://openalex.org/W4226022765","https://openalex.org/W4285079178","https://openalex.org/W4285411900","https://openalex.org/W4319341812","https://openalex.org/W4320713092","https://openalex.org/W4385080111","https://openalex.org/W4387490588","https://openalex.org/W4388469893","https://openalex.org/W4389076363","https://openalex.org/W4391019904","https://openalex.org/W4394966876","https://openalex.org/W4396909887","https://openalex.org/W4400234321","https://openalex.org/W4406754062","https://openalex.org/W4406856644"],"related_works":[],"abstract_inverted_index":{"Content-addressable":[0],"memory":[1,72],"(CAM)":[2],"is":[3],"regarded":[4],"as":[5],"an":[6],"attractive":[7],"solution":[8],"for":[9,75,195,204],"data-intensive":[10],"applications":[11],"with":[12,207],"high-density":[13,76],"search":[14],"demands.":[15],"To":[16,57],"further":[17],"improve":[18],"functional":[19],"flexibility":[20],"yet":[21],"at":[22],"a":[23,63,86,91,108,154,162,170,189],"low":[24],"cost,":[25],"several":[26],"CAM":[27,41,78,103,134,197],"macros":[28],"have":[29],"been":[30,151],"developed":[31],"to":[32,53,114,178],"support":[33],"multiple":[34],"bit-wise":[35],"logic":[36,205],"operations.":[37,82,104],"However,":[38],"conventional":[39],"SRAM-based":[40],"designs":[42],"are":[43],"constrained":[44],"by":[45],"the":[46,116,124,140,166,174,179,185],"large":[47],"bitcell":[48,89,167],"area,":[49],"posing":[50],"significant":[51],"challenges":[52],"achieve":[54],"higher":[55],"density.":[56],"address":[58],"this":[59],"issue,":[60],"we":[61,84,106,131],"propose":[62,85],"complementary":[64,94],"3T":[65],"(C3T)":[66],"based":[67],"embedded":[68],"dynamic":[69],"random":[70],"access":[71],"(eDRAM)":[73],"macro":[74,149,175],"dual-direction":[77,133],"searching":[79,135,199],"and":[80,101,136,169,201,213],"logic-in-memory":[81,137],"First,":[83],"compact":[87,109],"C3T":[88],"featuring":[90],"pair":[92],"of":[93,118,192,210],"decoupled":[95],"read":[96,100,125],"ports,":[97],"enabling":[98],"dual-port":[99],"efficient":[102],"Second,":[105],"present":[107],"dynamic-circuit-based":[110],"sense":[111],"amplifier":[112],"(DSA)":[113],"optimize":[115],"area":[117,168,176],"readout":[119],"peripheral":[120],"circuitry":[121],"while":[122],"mitigating":[123],"bit":[126],"line":[127],"saturation":[128],"issue.":[129],"Additionally,":[130],"implement":[132],"operations":[138,200],"exploiting":[139],"C3T-based":[141,147],"eDRAM":[142,148],"macro.":[143],"A":[144],"4":[145],"Kb":[146],"has":[150],"validated":[152],"in":[153,165,173],"commercial":[155],"40-nm":[156],"CMOS":[157],"process.":[158],"Post-layout":[159],"results":[160],"demonstrate":[161],"53%":[163],"reduction":[164,172],"58.1%":[171],"compared":[177],"state-of-the-art":[180],"6T":[181],"compute":[182],"SRAM.":[183],"Moreover,":[184],"proposed":[186],"design":[187],"achieves":[188],"maximum":[190],"frequency":[191],"578":[193],"MHz":[194,203],"binary":[196],"(BCAM)":[198],"694":[202],"operations,":[206],"energy":[208],"consumption":[209],"1.12":[211],"fJ/bit":[212],"26.8":[214],"fJ/bit,":[215],"respectively.":[216]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}
