{"id":"https://openalex.org/W4413464960","doi":"https://doi.org/10.1109/tcsi.2025.3593405","title":"Design for Slew-Rate in Multi-Stage CMOS OTAs","display_name":"Design for Slew-Rate in Multi-Stage CMOS OTAs","publication_year":2025,"publication_date":"2025-08-14","ids":{"openalex":"https://openalex.org/W4413464960","doi":"https://doi.org/10.1109/tcsi.2025.3593405"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3593405","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3593405","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://doi.org/10.1109/tcsi.2025.3593405","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056716766","display_name":"Mahmood A. Mohammed","orcid":"https://orcid.org/0000-0003-3947-6615"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mahmood A. Mohammed","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada"],"raw_orcid":"https://orcid.org/0000-0003-3947-6615","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071067911","display_name":"Feras Al-Dirini","orcid":"https://orcid.org/0000-0002-7703-2487"},"institutions":[{"id":"https://openalex.org/I204722609","display_name":"Queen's University","ror":"https://ror.org/02y72wh86","country_code":"CA","type":"education","lineage":["https://openalex.org/I204722609"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Feras Al-Dirini","raw_affiliation_strings":["School of Computing, Queen&#x2019;s University, Kingston, ON, Canada"],"raw_orcid":"https://orcid.org/0000-0002-7703-2487","affiliations":[{"raw_affiliation_string":"School of Computing, Queen&#x2019;s University, Kingston, ON, Canada","institution_ids":["https://openalex.org/I204722609"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034596339","display_name":"Ahmed S. Emara","orcid":"https://orcid.org/0000-0002-7329-7795"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Ahmed S. Emara","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada"],"raw_orcid":"https://orcid.org/0000-0002-7329-7795","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada","institution_ids":["https://openalex.org/I5023651"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083312864","display_name":"Gordon W. Roberts","orcid":"https://orcid.org/0000-0002-4880-0272"},"institutions":[{"id":"https://openalex.org/I5023651","display_name":"McGill University","ror":"https://ror.org/01pxwe438","country_code":"CA","type":"education","lineage":["https://openalex.org/I5023651"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Gordon W. Roberts","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada"],"raw_orcid":"https://orcid.org/0000-0002-4880-0272","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Integrated Microsystems Laboratory, McGill University, Montreal, QC, Canada","institution_ids":["https://openalex.org/I5023651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9471,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.73814433,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":97,"max":98},"biblio":{"volume":"73","issue":"2","first_page":"775","last_page":"788"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11472","display_name":"Analytical Chemistry and Sensors","score":0.975600004196167,"subfield":{"id":"https://openalex.org/subfields/1502","display_name":"Bioengineering"},"field":{"id":"https://openalex.org/fields/15","display_name":"Chemical Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11472","display_name":"Analytical Chemistry and Sensors","score":0.975600004196167,"subfield":{"id":"https://openalex.org/subfields/1502","display_name":"Bioengineering"},"field":{"id":"https://openalex.org/fields/15","display_name":"Chemical Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9746000170707703,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9664999842643738,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.8610689640045166},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6898333430290222},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5179364085197449},{"id":"https://openalex.org/keywords/stage","display_name":"Stage (stratigraphy)","score":0.45527830719947815},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4550091624259949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42704176902770996},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4102988839149475},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.371860533952713},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3297288715839386},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2517006993293762}],"concepts":[{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.8610689640045166},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6898333430290222},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5179364085197449},{"id":"https://openalex.org/C146357865","wikidata":"https://www.wikidata.org/wiki/Q1123245","display_name":"Stage (stratigraphy)","level":2,"score":0.45527830719947815},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4550091624259949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42704176902770996},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4102988839149475},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.371860533952713},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3297288715839386},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2517006993293762},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3593405","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3593405","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tcsi.2025.3593405","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3593405","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1643989195","https://openalex.org/W1950735355","https://openalex.org/W1972150182","https://openalex.org/W2004391179","https://openalex.org/W2041807775","https://openalex.org/W2099715640","https://openalex.org/W2101187277","https://openalex.org/W2110171809","https://openalex.org/W2117035579","https://openalex.org/W2120955105","https://openalex.org/W2124081222","https://openalex.org/W2125509130","https://openalex.org/W2154237706","https://openalex.org/W2166682505","https://openalex.org/W2167225414","https://openalex.org/W2513579149","https://openalex.org/W2551453206","https://openalex.org/W2559152050","https://openalex.org/W3006464937","https://openalex.org/W3011653750","https://openalex.org/W3011936957","https://openalex.org/W3026476728","https://openalex.org/W3114490134","https://openalex.org/W3158719468","https://openalex.org/W3158881598","https://openalex.org/W3208014417","https://openalex.org/W4312540172","https://openalex.org/W4386869804","https://openalex.org/W4394892280","https://openalex.org/W4402754018","https://openalex.org/W4403106863"],"related_works":["https://openalex.org/W2014419659","https://openalex.org/W2075569182","https://openalex.org/W170188723","https://openalex.org/W2115314666","https://openalex.org/W2099162222","https://openalex.org/W2029904754","https://openalex.org/W1989271320","https://openalex.org/W2031160685","https://openalex.org/W2070694218","https://openalex.org/W2532822217"],"abstract_inverted_index":{"Cascading":[0],"gain":[1,17,28,59],"stages":[2,60],"in":[3,13,67,90,107,125,225,235,242],"CMOS":[4,109,189,198,244],"Operational":[5],"Transconductance":[6],"Amplifiers":[7],"(OTAs)":[8],"has":[9,70],"become":[10],"a":[11,44,96,102,116,184,187,196,236],"necessity":[12],"applications":[14,37],"with":[15,178,192],"high":[16],"requirements,":[18],"where":[19],"the":[20,26,55,62,83,86,113,122,137,146,151,158,161,204,222,227],"contribution":[21],"of":[22,35,57,85,115,140,183,195],"each":[23,141],"stage":[24],"to":[25,50,73,82],"overall":[27,63,152],"is":[29],"well-known":[30],"and":[31,133,170,181,186,191,215,232],"carefully":[32,76],"designed.":[33],"Many":[34],"these":[36,91],"also":[38],"impose":[39],"requirements":[40],"on":[41,61,145,167],"speed,":[42],"including":[43],"minimum":[45],"Slew-Rate":[46,124],"(<italic":[47],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[48,65,105,154,163,218,230,239],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SR</i>)":[49],"ensure":[51],"signal":[52],"fidelity,":[53],"however":[54],"impact":[56],"individual":[58,131],"<italic":[64,104,153,162,217,229],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SR</i>":[66,106,164,219,240],"multi-stage":[68,108,126,243],"OTAs":[69],"been":[71],"difficult":[72],"characterize\u2013let":[74],"alone":[75],"design.":[77],"The":[78,128,207],"difficulty":[79],"arises":[80],"due":[81],"complexity":[84],"compensation":[87,174],"networks":[88],"involved":[89],"OTAs.":[92,127,245],"This":[93],"paper":[94],"presents":[95],"systematic":[97,237],"design":[98],"approach":[99,241],"for":[100,120,202],"achieving":[101],"target":[103],"OTAs,":[110],"enabled":[111],"through":[112],"utility":[114,234],"novel":[117],"analytical":[118],"model":[119,129,159],"estimating":[121,226],"lower-bound":[123,228],"evaluates":[130],"currents":[132],"equivalent":[134],"capacitances":[135],"at":[136],"output":[138],"node":[139,148],"stage,":[142],"providing":[143],"insights":[144],"dominant":[147],"slowing":[149],"down":[150],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SR</i>.":[155],"For":[156],"generality,":[157],"establishes":[160],"analysis":[165],"based":[166],"N-stage":[168],"designs,":[169,177],"considers":[171],"widely":[172],"employed":[173],"networks.":[175],"Example":[176],"post-layout":[179,193],"simulations":[180,194],"measurements":[182],"3-":[185],"4-stage":[188],"OTA,":[190,199],"5-stage":[197],"are":[200],"presented":[201],"validating":[203],"model\u2019s":[205,223],"utility.":[206],"results":[208],"show":[209],"strong":[210],"agreement":[211],"between":[212],"theoretical,":[213],"simulated,":[214],"measured":[216],"values,":[220],"confirming":[221],"reliability":[224],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">SR</i>,":[231],"its":[233],"design-for-<italic":[238]},"counts_by_year":[{"year":2026,"cited_by_count":2}],"updated_date":"2026-02-02T03:55:41.653505","created_date":"2025-10-10T00:00:00"}
