{"id":"https://openalex.org/W4412567357","doi":"https://doi.org/10.1109/tcsi.2025.3584247","title":"Memristor-Based Circuit Implementation and Circuitry Optimized Algorithm for Mamba Language Network","display_name":"Memristor-Based Circuit Implementation and Circuitry Optimized Algorithm for Mamba Language Network","publication_year":2025,"publication_date":"2025-07-22","ids":{"openalex":"https://openalex.org/W4412567357","doi":"https://doi.org/10.1109/tcsi.2025.3584247"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3584247","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3584247","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056899765","display_name":"J. J. Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I74525822","display_name":"Hubei University of Technology","ror":"https://ror.org/02d3fj342","country_code":"CN","type":"education","lineage":["https://openalex.org/I74525822"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junming Zhang","raw_affiliation_strings":["School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0009-0006-9387-6010","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I74525822"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045568512","display_name":"Z. M. Sheng","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zheyuan Sheng","raw_affiliation_strings":["Ming Hsieh Department of Electrical and Computer Engineering, Viterbi School of Engineering, University of Southern California, Los Angeles, CA, USA"],"raw_orcid":"https://orcid.org/0009-0008-4711-0174","affiliations":[{"raw_affiliation_string":"Ming Hsieh Department of Electrical and Computer Engineering, Viterbi School of Engineering, University of Southern California, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024360832","display_name":"Huajun Sun","orcid":"https://orcid.org/0000-0003-0755-5247"},"institutions":[{"id":"https://openalex.org/I74525822","display_name":"Hubei University of Technology","ror":"https://ror.org/02d3fj342","country_code":"CN","type":"education","lineage":["https://openalex.org/I74525822"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huajun Sun","raw_affiliation_strings":["School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0000-0003-0755-5247","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I74525822"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059375680","display_name":"Chuanbo Zhu","orcid":"https://orcid.org/0000-0002-6441-1162"},"institutions":[{"id":"https://openalex.org/I4210138186","display_name":"Wuhan National Laboratory for Optoelectronics","ror":"https://ror.org/03c9ncn37","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210138186"]},{"id":"https://openalex.org/I47720641","display_name":"Huazhong University of Science and Technology","ror":"https://ror.org/00p991c53","country_code":"CN","type":"education","lineage":["https://openalex.org/I47720641"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chuanbo Zhu","raw_affiliation_strings":["Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0000-0002-6441-1162","affiliations":[{"raw_affiliation_string":"Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I4210138186","https://openalex.org/I47720641"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100780222","display_name":"Liangyu Chen","orcid":"https://orcid.org/0009-0008-3490-424X"},"institutions":[{"id":"https://openalex.org/I93860229","display_name":"Politecnico di Milano","ror":"https://ror.org/01nffqt88","country_code":"IT","type":"education","lineage":["https://openalex.org/I93860229"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Liangyu Chen","raw_affiliation_strings":["Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy","institution_ids":["https://openalex.org/I93860229"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068556196","display_name":"Zhenyu Hu","orcid":"https://orcid.org/0000-0003-1403-1732"},"institutions":[{"id":"https://openalex.org/I111088046","display_name":"Boston University","ror":"https://ror.org/05qwgg493","country_code":"US","type":"education","lineage":["https://openalex.org/I111088046"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhenyu Hu","raw_affiliation_strings":["College of Engineering, Boston University, Boston, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Engineering, Boston University, Boston, MA, USA","institution_ids":["https://openalex.org/I111088046"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100607861","display_name":"Xiangshui Miao","orcid":"https://orcid.org/0000-0002-5621-5495"},"institutions":[{"id":"https://openalex.org/I74525822","display_name":"Hubei University of Technology","ror":"https://ror.org/02d3fj342","country_code":"CN","type":"education","lineage":["https://openalex.org/I74525822"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiangshui Miao","raw_affiliation_strings":["School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China"],"raw_orcid":"https://orcid.org/0000-0002-5621-5495","affiliations":[{"raw_affiliation_string":"School of Integrated Circuits, Hubei Key Laboratory of Advanced Memories, Hubei Engineering Research Center on Microelectronics, Huazhong University of Science and Technology, Wuhan, China","institution_ids":["https://openalex.org/I74525822"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.5254,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68002304,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":98},"biblio":{"volume":"73","issue":"1","first_page":"425","last_page":"438"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9090999960899353,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9090999960899353,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.8419739603996277},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5923455953598022},{"id":"https://openalex.org/keywords/network-analysis","display_name":"Network analysis","score":0.4528657793998718},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.42906489968299866},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.393378883600235},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31294941902160645},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18826958537101746}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.8419739603996277},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5923455953598022},{"id":"https://openalex.org/C32946077","wikidata":"https://www.wikidata.org/wiki/Q618079","display_name":"Network analysis","level":2,"score":0.4528657793998718},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42906489968299866},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.393378883600235},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31294941902160645},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18826958537101746}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/tcsi.2025.3584247","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3584247","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},{"id":"pmh:oai:re.public.polimi.it:11311/1296001","is_oa":false,"landing_page_url":"https://hdl.handle.net/11311/1296001","pdf_url":null,"source":{"id":"https://openalex.org/S4306400312","display_name":"Virtual Community of Pathological Anatomy (University of Castilla La Mancha)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I79189158","host_organization_name":"University of Castilla-La Mancha","host_organization_lineage":["https://openalex.org/I79189158"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3018545633","display_name":null,"funder_award_id":"62474074","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W4229452466","https://openalex.org/W2966276069","https://openalex.org/W2304829496","https://openalex.org/W2358307108","https://openalex.org/W3031124155","https://openalex.org/W2463286374","https://openalex.org/W2052332160","https://openalex.org/W2204001882","https://openalex.org/W190448578"],"abstract_inverted_index":{"Language":[0],"networks":[1],"are":[2],"crucial":[3],"in":[4,52,139,163],"artificial":[5],"intelligence,":[6],"with":[7],"the":[8,19,28,37,68,105,166,180],"novel":[9],"Mamba":[10,29,50,69],"architecture":[11],"significantly":[12],"reducing":[13],"computations":[14,40,147],"and":[15,41,71,89,107,120,127,136,148,153,176,195],"consumption":[16,178],"compared":[17],"to":[18,36],"traditional":[20],"transformer":[21],"network.":[22],"However,":[23],"a":[24,63,73,188],"full-circuit":[25,65],"implementation":[26,66,82,129],"of":[27,39,67,109,170],"network":[30,70],"has":[31],"not":[32],"been":[33],"proposed":[34,142,181],"due":[35],"complexity":[38],"data":[42],"storage.":[43,155],"Additionally,":[44],"optimized":[45],"hardware-aware":[46,131],"parallel":[47,134],"algorithms":[48],"for":[49,78,95,104,115,130,191],"inference":[51],"circuits":[53,103,114],"remain":[54],"undeveloped.":[55],"This":[56],"work":[57],"addresses":[58],"these":[59],"challenges":[60],"by":[61],"presenting":[62],"memristor-based":[64],"introducing":[72],"computing-in-memory":[74],"parallel-aware":[75],"algorithm":[76,126],"tailored":[77],"circuit-level":[79],"inference.":[80],"The":[81,141],"includes:":[83],"1)":[84],"Standard":[85],"1T1M":[86],"memristor":[87,93],"crossbar":[88,94],"depthwise":[90],"separable":[91],"convolution":[92],"different":[96],"convolutions.":[97],"2)":[98],"Computing-in-memory":[99],"implicit":[100],"latent":[101,110],"state":[102],"computation":[106,172],"transition":[108],"states.":[111],"3)":[112],"Functional":[113],"SiLU":[116],"activation,":[117],"RMS":[118],"normalization,":[119],"multi-layer":[121],"multiply-accumulate":[122],"operations.":[123],"4)":[124],"Optimized":[125],"circuit":[128,143,174,193],"inference,":[132],"achieving":[133],"scanning":[135],"hardware":[137],"awareness":[138],"circuits.":[140],"enables":[144],"analog":[145,171],"signal":[146],"eliminates":[149],"redundant":[150],"analog-to-digital":[151],"conversions":[152],"intermediate":[154],"A":[156],"basic":[157],"single-sentence":[158],"generation":[159,198],"task":[160],"was":[161],"simulated":[162],"PSPICE,":[164],"validating":[165],"circuit\u2019s":[167,182],"correctness.":[168],"Analyses":[169],"accuracy,":[173],"stability,":[175],"power":[177],"demonstrate":[179],"advantages,":[183],"highlighting":[184],"its":[185],"potential":[186],"as":[187],"fundamental":[189],"module":[190],"large-scale":[192],"integration":[194],"complex":[196],"text":[197],"tasks.":[199]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-06-16T09:24:06.705377","created_date":"2025-10-10T00:00:00"}
