{"id":"https://openalex.org/W6903316902","doi":"https://doi.org/10.1109/tcsi.2025.3583422","title":"An Ultrasound Transducer Analog Front-End With dB-Linear Time-Gain Compensation Using Translinear Loop Principle","display_name":"An Ultrasound Transducer Analog Front-End With dB-Linear Time-Gain Compensation Using Translinear Loop Principle","publication_year":2025,"publication_date":"2025-07-10","ids":{"openalex":"https://openalex.org/W6903316902","doi":"https://doi.org/10.1109/tcsi.2025.3583422"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3583422","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3583422","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":null,"display_name":"Siqi Wang","orcid":"https://orcid.org/0000-0002-5699-6172"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Siqi Wang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Lei Xie","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lei Xie","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jiabin Zhang","orcid":null},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiabin Zhang","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Zhenghao Lu","orcid":"https://orcid.org/0000-0002-3913-3842"},"institutions":[{"id":"https://openalex.org/I3923682","display_name":"Soochow University","ror":"https://ror.org/05t8y2r12","country_code":"CN","type":"education","lineage":["https://openalex.org/I3923682"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhenghao Lu","raw_affiliation_strings":["School of Electronics and Information, Soochow University, Suzhou, China"],"affiliations":[{"raw_affiliation_string":"School of Electronics and Information, Soochow University, Suzhou, China","institution_ids":["https://openalex.org/I3923682"]}]},{"author_position":"last","author":{"id":null,"display_name":"Xiaopeng Yu","orcid":"https://orcid.org/0000-0002-4531-6645"},"institutions":[{"id":"https://openalex.org/I4210092088","display_name":"Zhejiang Province Institute of Architectural Design and Research","ror":"https://ror.org/00f89ms08","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210092088"]},{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaopeng Yu","raw_affiliation_strings":["Institute of VLSI Design, Zhejiang University, Hangzhou, China"],"affiliations":[{"raw_affiliation_string":"Institute of VLSI Design, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210092088","https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.41164857,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"72","issue":"11","first_page":"6399","last_page":"6410"},"is_retracted":false,"is_paratext":false,"is_xpac":true,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.6450999975204468,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.6450999975204468,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10727","display_name":"Ultrasound Imaging and Elastography","score":0.1356000006198883,"subfield":{"id":"https://openalex.org/subfields/2741","display_name":"Radiology, Nuclear Medicine and Imaging"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.11999999731779099,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/open-loop-gain","display_name":"Open-loop gain","score":0.7391999959945679},{"id":"https://openalex.org/keywords/automatic-gain-control","display_name":"Automatic gain control","score":0.612500011920929},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6043000221252441},{"id":"https://openalex.org/keywords/loop-gain","display_name":"Loop gain","score":0.5774999856948853},{"id":"https://openalex.org/keywords/phase-margin","display_name":"Phase margin","score":0.5587999820709229},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5264000296592712},{"id":"https://openalex.org/keywords/frequency-compensation","display_name":"Frequency compensation","score":0.4740000069141388},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.46219998598098755},{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.44909998774528503},{"id":"https://openalex.org/keywords/buffer-amplifier","display_name":"Buffer amplifier","score":0.4375}],"concepts":[{"id":"https://openalex.org/C143931264","wikidata":"https://www.wikidata.org/wiki/Q5932986","display_name":"Open-loop gain","level":5,"score":0.7391999959945679},{"id":"https://openalex.org/C177502760","wikidata":"https://www.wikidata.org/wiki/Q782524","display_name":"Automatic gain control","level":4,"score":0.612500011920929},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6043000221252441},{"id":"https://openalex.org/C199943209","wikidata":"https://www.wikidata.org/wiki/Q1271153","display_name":"Loop gain","level":3,"score":0.5774999856948853},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5655999779701233},{"id":"https://openalex.org/C81455027","wikidata":"https://www.wikidata.org/wiki/Q7180955","display_name":"Phase margin","level":5,"score":0.5587999820709229},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5264000296592712},{"id":"https://openalex.org/C131782439","wikidata":"https://www.wikidata.org/wiki/Q1455581","display_name":"Frequency compensation","level":4,"score":0.4740000069141388},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.46219998598098755},{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.44909998774528503},{"id":"https://openalex.org/C127749002","wikidata":"https://www.wikidata.org/wiki/Q978470","display_name":"Buffer amplifier","level":4,"score":0.4375},{"id":"https://openalex.org/C186886427","wikidata":"https://www.wikidata.org/wiki/Q5441213","display_name":"Feedback loop","level":2,"score":0.3937999904155731},{"id":"https://openalex.org/C98377741","wikidata":"https://www.wikidata.org/wiki/Q7236514","display_name":"Power gain","level":4,"score":0.3928000032901764},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.38350000977516174},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.3531999886035919},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3400999903678894},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3391999900341034},{"id":"https://openalex.org/C76265683","wikidata":"https://www.wikidata.org/wiki/Q1117035","display_name":"Negative feedback amplifier","level":5,"score":0.3240000009536743},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31690001487731934},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3138999938964844},{"id":"https://openalex.org/C148043351","wikidata":"https://www.wikidata.org/wiki/Q4456944","display_name":"Current (fluid)","level":2,"score":0.31060001254081726},{"id":"https://openalex.org/C56318395","wikidata":"https://www.wikidata.org/wiki/Q215928","display_name":"Transducer","level":2,"score":0.30239999294281006},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3012999892234802},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.2994999885559082},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.29580000042915344},{"id":"https://openalex.org/C2777271169","wikidata":"https://www.wikidata.org/wiki/Q190169","display_name":"Analog-to-digital converter","level":3,"score":0.29260000586509705},{"id":"https://openalex.org/C61829901","wikidata":"https://www.wikidata.org/wiki/Q769152","display_name":"High-gain antenna","level":2,"score":0.29030001163482666},{"id":"https://openalex.org/C58760974","wikidata":"https://www.wikidata.org/wiki/Q5517216","display_name":"Gain compression","level":4,"score":0.2840999960899353},{"id":"https://openalex.org/C151376022","wikidata":"https://www.wikidata.org/wiki/Q168698","display_name":"Exponential function","level":2,"score":0.2669000029563904},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.26409998536109924},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.2605000138282776},{"id":"https://openalex.org/C38566628","wikidata":"https://www.wikidata.org/wiki/Q1634194","display_name":"Gain\u2013bandwidth product","level":5,"score":0.26030001044273376}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3583422","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3583422","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G7545774241","display_name":null,"funder_award_id":"2022YFB3205003","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":33,"referenced_works":["https://openalex.org/W146068009","https://openalex.org/W1510054928","https://openalex.org/W1545485620","https://openalex.org/W2010026422","https://openalex.org/W2018809497","https://openalex.org/W2060445937","https://openalex.org/W2101809138","https://openalex.org/W2116973457","https://openalex.org/W2140576958","https://openalex.org/W2141707986","https://openalex.org/W2143165612","https://openalex.org/W2216062291","https://openalex.org/W2569197793","https://openalex.org/W2569264893","https://openalex.org/W2949955856","https://openalex.org/W2954033206","https://openalex.org/W2964612387","https://openalex.org/W3015935836","https://openalex.org/W3026039463","https://openalex.org/W3029030950","https://openalex.org/W3088065608","https://openalex.org/W3114372533","https://openalex.org/W3120608015","https://openalex.org/W3127599739","https://openalex.org/W3133542079","https://openalex.org/W3135849680","https://openalex.org/W3175717350","https://openalex.org/W3176092241","https://openalex.org/W3209823690","https://openalex.org/W4256373438","https://openalex.org/W4293811929","https://openalex.org/W4377235202","https://openalex.org/W4387042049"],"related_works":[],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"an":[3,118],"ultrasound":[4],"analog":[5],"front-end":[6],"(AFE)":[7],"circuit":[8],"featuring":[9],"continuous":[10],"time-gain":[11],"compensation":[12],"(TGC)":[13],"based":[14],"on":[15],"a":[16,24,30,51,68,79,95,103,125,129],"variable-gain":[17],"current":[18,27,31,54],"amplifier":[19],"(VGCA).":[20],"The":[21,41,62,87],"AFE":[22,64],"comprises":[23],"class-AB":[25],"input":[26],"buffer":[28],"and":[29],"gain":[32,42,45,60,97,104,113],"stage":[33,46],"realized":[34],"by":[35,50],"the":[36,44,58,92,112,115],"translinear":[37],"(TL)":[38],"loop":[39],"principle.":[40],"of":[43,82,99,106,121,132],"is":[47,65],"precisely":[48],"controlled":[49],"novel":[52],"exponential":[53],"generator":[55],"to":[56],"achieve":[57],"dB-linear":[59,96],"characteristic.":[61],"proposed":[63],"fabricated":[66],"in":[67],"0.13-<inline-formula":[69],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[70,85],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[71],"<tex-math":[72],"notation=\"LaTeX\">$\\mu":[73],"$</tex-math>":[74],"</inline-formula>m":[75],"CMOS":[76],"technology":[77],"with":[78,102,128],"core":[80],"area":[81],"0.08":[83],"mm<sup":[84],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>.":[86],"measurement":[88],"results":[89],"show":[90],"that":[91],"VGCA":[93,116],"has":[94],"range":[98],"37.3":[100],"dB":[101],"error":[105],"less":[107],"than":[108],"\u00b10.7":[109],"dB.":[110],"Within":[111],"range,":[114],"consumes":[117],"average":[119],"power":[120],"0.65":[122],"mW":[123],"from":[124],"1.2V":[126],"supply,":[127],"minimum":[130],"bandwidth":[131],"1.61":[133],"MHz.":[134]},"counts_by_year":[],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}