{"id":"https://openalex.org/W4408697438","doi":"https://doi.org/10.1109/tcsi.2025.3550314","title":"Memory Technologies for Crossbar Array Design: A Comparative Evaluation of Their Impact on DNN Accuracy","display_name":"Memory Technologies for Crossbar Array Design: A Comparative Evaluation of Their Impact on DNN Accuracy","publication_year":2025,"publication_date":"2025-03-21","ids":{"openalex":"https://openalex.org/W4408697438","doi":"https://doi.org/10.1109/tcsi.2025.3550314"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3550314","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3550314","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102694093","display_name":"Jeffry Victor","orcid":"https://orcid.org/0000-0002-9487-8177"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffry Victor","raw_affiliation_strings":["Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"raw_orcid":"https://orcid.org/0000-0002-9487-8177","affiliations":[{"raw_affiliation_string":"Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5115603288","display_name":"Chunguang Wang","orcid":"https://orcid.org/0009-0001-1275-0680"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chunguang Wang","raw_affiliation_strings":["Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"raw_orcid":"https://orcid.org/0009-0001-1275-0680","affiliations":[{"raw_affiliation_string":"Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044276472","display_name":"Sumeet Kumar Gupta","orcid":"https://orcid.org/0000-0001-5609-9722"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sumeet Kumar Gupta","raw_affiliation_strings":["Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA"],"raw_orcid":"https://orcid.org/0000-0001-5609-9722","affiliations":[{"raw_affiliation_string":"Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I219193219"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0419185,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"72","issue":"10","first_page":"5708","last_page":"5721"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12029","display_name":"DNA and Biological Computing","score":0.98089998960495,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},"topics":[{"id":"https://openalex.org/T12029","display_name":"DNA and Biological Computing","score":0.98089998960495,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12162","display_name":"Cellular Automata and Applications","score":0.9699000120162964,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11392","display_name":"Energy Harvesting in Wireless Networks","score":0.9696000218391418,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.7403155565261841},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5642951726913452},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45951998233795166},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2555145025253296},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2338619828224182}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.7403155565261841},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5642951726913452},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45951998233795166},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2555145025253296},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2338619828224182}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3550314","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3550314","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":30,"referenced_works":["https://openalex.org/W2088797290","https://openalex.org/W2096199318","https://openalex.org/W2096445739","https://openalex.org/W2113809410","https://openalex.org/W2194775991","https://openalex.org/W2288519604","https://openalex.org/W2329040051","https://openalex.org/W2787759178","https://openalex.org/W2889456398","https://openalex.org/W2893163116","https://openalex.org/W2912765464","https://openalex.org/W2945561934","https://openalex.org/W2946206667","https://openalex.org/W2966878541","https://openalex.org/W2983353765","https://openalex.org/W3091835145","https://openalex.org/W3136138154","https://openalex.org/W3138990781","https://openalex.org/W3176606713","https://openalex.org/W3177592084","https://openalex.org/W3177907605","https://openalex.org/W3187831751","https://openalex.org/W3198405160","https://openalex.org/W4245731639","https://openalex.org/W4293144785","https://openalex.org/W4312121016","https://openalex.org/W4312464450","https://openalex.org/W4312560809","https://openalex.org/W4385190118","https://openalex.org/W4391428254"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2899084033","https://openalex.org/W2748952813","https://openalex.org/W2145932742","https://openalex.org/W1874409533","https://openalex.org/W2554791727","https://openalex.org/W1981395029","https://openalex.org/W2108083791","https://openalex.org/W4250137794","https://openalex.org/W2063341228"],"abstract_inverted_index":{"In-memory":[0],"computing":[1],"(IMC)":[2],"using":[3],"synaptic":[4,162],"crossbar":[5,50,126],"arrays":[6,127],"offers":[7],"a":[8,64,75,90,153],"promising":[9],"pathway":[10],"toward":[11],"energy-efficient":[12],"deep":[13],"neural":[14],"network":[15],"(DNN)":[16],"accelerators.":[17],"The":[18],"potential":[19],"of":[20,26,78,97,131,142,161,171,197,261,283],"IMC":[21],"is":[22],"accentuated":[23],"by":[24],"virtue":[25],"IMC-compatible":[27],"CMOS":[28],"and":[29,94,108,128,149,164,183,204,207,231,252,270,279],"non-volatile":[30],"memory":[31],"technologies,":[32,80],"which":[33,46],"offer":[34],"various":[35],"appealing":[36],"features.":[37],"However,":[38],"each":[39,143,198,284],"technology":[40,199,285],"suffers":[41],"from":[42],"its":[43],"own":[44],"issues,":[45],"along":[47],"with":[48,74,219,250],"the":[49,54,70,116,122,129,132,168,179,188,195,236,281],"non-idealities,":[51,72],"significantly":[52],"impair":[53],"DNN":[55,135,189,213],"accuracy,":[56,238],"especially":[57,239],"in":[58,125],"scaled":[59],"technologies.":[60,173],"In":[61],"this":[62,86],"context,":[63],"comprehensive":[65],"cross-layer":[66,154],"optimization":[67,141],"to":[68,200,226,235,259,286],"address":[69,85],"hardware":[71],"coupled":[73],"comparative":[76,95],"evaluation":[77,96],"optimized":[79,223],"remains":[81],"largely":[82],"unexplored.":[83],"To":[84],"need,":[87],"we":[88,166,175,193,264],"conduct":[89,139],"design":[91,210],"space":[92],"exploration":[93],"four":[98],"prominent":[99],"technologies\u20148T":[100],"SRAM,":[101],"ferroelectric":[102],"transistors":[103],"(FeFETs),":[104],"resistive":[105],"RAM":[106,112],"(ReRAM),":[107],"spin-orbit":[109],"torque":[110],"magnetic":[111],"(SOT-MRAM)":[113],"\u2013":[114],"at":[115],"7nm":[117],"node.":[118],"We":[119,138],"focus":[120],"on":[121,134,178],"computational":[123],"robustness":[124],"influence":[130],"technologies":[133],"inference":[136,169],"accuracy.":[137,190,214],"IMC-driven":[140],"technology,":[144],"accounting":[145],"for":[146,217,240],"both":[147],"device-":[148],"circuit-level":[150],"non-idealities.":[151],"Using":[152],"simulation":[155],"framework":[156],"that":[157,186,222,260],"integrates":[158],"physical":[159],"models":[160],"devices":[163],"interconnects,":[165],"compare":[167,280],"accuracy":[170],"these":[172,287],"Further,":[174],"throw":[176],"light":[177],"unique":[180],"device":[181],"attributes":[182],"device-circuit":[184],"interactions":[185],"impact":[187,212],"Following":[191],"this,":[192],"analyze":[194],"response":[196,282],"array":[201],"size,":[202],"bit-slice,":[203],"dataset/network":[205],"complexity":[206],"how":[208],"such":[209],"knob":[211],"Our":[215],"results":[216],"ResNet-20":[218],"CIFAR-10":[220],"show":[221],"FeFETs,":[224],"due":[225],"their":[227],"compact":[228],"bit-cell":[229],"layout":[230],"high":[232],"distinguishability,":[233],"lead":[234],"highest":[237],"large":[241],"arrays.":[242],"For":[243],"more":[244],"complex":[245],"datasets":[246],"(such":[247],"as":[248,276],"ResNet-50":[249],"CIFAR-100)":[251],"larger":[253],"bit-slices,":[254],"ReRAM":[255],"achieves":[256],"performance":[257],"comparable":[258],"FeFET.":[262],"Lastly,":[263],"evaluate":[265],"Partial":[266],"Wordline":[267],"Activation":[268],"(PWA)":[269],"propose":[271],"custom":[272],"ADC":[273],"reference":[274],"levels":[275],"non-ideality-mitigating":[277],"solutions":[278],"techniques.":[288]},"counts_by_year":[],"updated_date":"2025-12-28T23:10:05.387466","created_date":"2025-10-10T00:00:00"}