{"id":"https://openalex.org/W4406170465","doi":"https://doi.org/10.1109/tcsi.2025.3525619","title":"A Predictive SAR ADC Architecture","display_name":"A Predictive SAR ADC Architecture","publication_year":2025,"publication_date":"2025-01-08","ids":{"openalex":"https://openalex.org/W4406170465","doi":"https://doi.org/10.1109/tcsi.2025.3525619"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2025.3525619","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3525619","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5112913836","display_name":"Matias Jara","orcid":"https://orcid.org/0009-0002-7755-2738"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Matias Jara","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA","Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, Irvine, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, Irvine, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049567991","display_name":"Behzad Razavi","orcid":"https://orcid.org/0000-0003-1168-9205"},"institutions":[{"id":"https://openalex.org/I161318765","display_name":"University of California, Los Angeles","ror":"https://ror.org/046rm7j60","country_code":"US","type":"education","lineage":["https://openalex.org/I161318765"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Behzad Razavi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA","institution_ids":["https://openalex.org/I161318765"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5112913836"],"corresponding_institution_ids":["https://openalex.org/I161318765"],"apc_list":null,"apc_paid":null,"fwci":4.1939,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.93128293,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":"72","issue":"9","first_page":"4513","last_page":"4526"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.8257910013198853},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6499300003051758},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6469809412956238},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5567794442176819},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5135447978973389},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4973008930683136},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.42270082235336304},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3563886880874634},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2756199240684509},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2693132162094116},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2267555594444275}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.8257910013198853},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6499300003051758},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6469809412956238},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5567794442176819},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5135447978973389},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4973008930683136},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.42270082235336304},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3563886880874634},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2756199240684509},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2693132162094116},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2267555594444275},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2025.3525619","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2025.3525619","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5600000023841858,"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320313834","display_name":"Fulbright Chile","ror":null},{"id":"https://openalex.org/F4320331146","display_name":"Agencia Nacional de Investigaci\u00f3n y Desarrollo","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1528298974","https://openalex.org/W1806144281","https://openalex.org/W1964087719","https://openalex.org/W1976807891","https://openalex.org/W2039454339","https://openalex.org/W2057996228","https://openalex.org/W2062684659","https://openalex.org/W2097216498","https://openalex.org/W2101004723","https://openalex.org/W2107169806","https://openalex.org/W2126190772","https://openalex.org/W2147723118","https://openalex.org/W2155589054","https://openalex.org/W2157944808","https://openalex.org/W2286453822","https://openalex.org/W2343222450","https://openalex.org/W2525108866","https://openalex.org/W2592800647","https://openalex.org/W2785229656","https://openalex.org/W2964671960","https://openalex.org/W3110546428","https://openalex.org/W4300994846","https://openalex.org/W4323896642","https://openalex.org/W4376133976","https://openalex.org/W4392745718","https://openalex.org/W4401507842"],"related_works":["https://openalex.org/W2278942241","https://openalex.org/W2368405386","https://openalex.org/W1977749038","https://openalex.org/W1641489184","https://openalex.org/W3004044036","https://openalex.org/W2792167570","https://openalex.org/W2290076986","https://openalex.org/W2071924372","https://openalex.org/W4284685595","https://openalex.org/W2377552037"],"abstract_inverted_index":{"A":[0],"SAR":[1,31],"architecture":[2],"is":[3,54,66],"proposed":[4],"that":[5,56],"employs":[6],"a":[7,47,62,87,106],"predictive":[8],"technique":[9],"to":[10,36,73,111],"increase":[11],"the":[12,19,25,30,70],"conversion":[13,115],"speed.":[14],"In":[15],"this":[16],"new":[17],"technique,":[18],"comparator":[20,39],"operates":[21],"in":[22,61,83],"parallel":[23],"with":[24],"logic":[26],"and":[27,49,76,105],"DAC,":[28],"reducing":[29],"timing":[32],"budget":[33],"per":[34,114],"cycle":[35],"only":[37],"one":[38],"decision":[40],"time":[41],"plus":[42],"its":[43],"clock":[44,48,58,72],"generation.":[45],"Moreover,":[46],"input":[50,100],"signal":[51],"distribution":[52],"method":[53],"presented":[55],"improves":[57],"phase":[59],"matching":[60],"time-interleaved":[63],"system.":[64],"This":[65],"accomplished":[67],"by":[68],"delivering":[69],"primary":[71],"each":[74],"channel":[75],"generating":[77],"their":[78],"interleaved":[79],"phases":[80],"locally.":[81],"Realized":[82],"28-nm":[84],"CMOS":[85],"technology,":[86],"6-bit":[88],"10-GS/s":[89],"17.6-mW":[90],"prototype":[91],"achieves":[92],"an":[93,99],"SNDR":[94],"of":[95,102,108],"31.2":[96],"dB":[97],"at":[98],"frequency":[101],"4.96":[103],"GHz":[104],"figure":[107],"merit":[109],"equal":[110],"59":[112],"fJ":[113],"step.":[116]},"counts_by_year":[{"year":2025,"cited_by_count":6}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
