{"id":"https://openalex.org/W4405520273","doi":"https://doi.org/10.1109/tcsi.2024.3511955","title":"In-Memory Implementation of an Approximate Adder With Reduced Latency and Error","display_name":"In-Memory Implementation of an Approximate Adder With Reduced Latency and Error","publication_year":2024,"publication_date":"2024-12-18","ids":{"openalex":"https://openalex.org/W4405520273","doi":"https://doi.org/10.1109/tcsi.2024.3511955"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3511955","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3511955","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5077009918","display_name":"Vijaya Lakshmi","orcid":"https://orcid.org/0000-0001-7300-6284"},"institutions":[{"id":"https://openalex.org/I4210109292","display_name":"Indian Institute of Technology Tirupati","ror":"https://ror.org/01xtkxh20","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210109292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vijaya Lakshmi","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology at Tirupati, Tirupati, India"],"raw_orcid":"https://orcid.org/0000-0001-7300-6284","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology at Tirupati, Tirupati, India","institution_ids":["https://openalex.org/I4210109292"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025451495","display_name":"Vikramkumar Pudi","orcid":"https://orcid.org/0000-0003-3992-0624"},"institutions":[{"id":"https://openalex.org/I4210109292","display_name":"Indian Institute of Technology Tirupati","ror":"https://ror.org/01xtkxh20","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210109292"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Vikramkumar Pudi","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology at Tirupati, Tirupati, India"],"raw_orcid":"https://orcid.org/0000-0003-3992-0624","affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology at Tirupati, Tirupati, India","institution_ids":["https://openalex.org/I4210109292"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023839129","display_name":"John Reuben","orcid":"https://orcid.org/0000-0002-7891-4975"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"John Reuben","raw_affiliation_strings":["Chair of Computer Architecture, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany"],"raw_orcid":"https://orcid.org/0000-0002-7891-4975","affiliations":[{"raw_affiliation_string":"Chair of Computer Architecture, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2495,"currency":"USD","value_usd":2495},"apc_paid":null,"fwci":0.6251,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71086262,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":97},"biblio":{"volume":"72","issue":"5","first_page":"2128","last_page":"2138"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9707000255584717,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9659000039100647,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8050980567932129},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6258550882339478},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.5100565552711487},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5062233805656433},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4142875671386719},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4070599377155304},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2106064260005951},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16026344895362854},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13489994406700134}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8050980567932129},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6258550882339478},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.5100565552711487},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5062233805656433},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4142875671386719},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4070599377155304},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2106064260005951},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16026344895362854},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13489994406700134}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3511955","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3511955","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1979504894","https://openalex.org/W1999085092","https://openalex.org/W2004782555","https://openalex.org/W2005652364","https://openalex.org/W2033224922","https://openalex.org/W2083156986","https://openalex.org/W2131023370","https://openalex.org/W2149471804","https://openalex.org/W2329040051","https://openalex.org/W2609332101","https://openalex.org/W2800491064","https://openalex.org/W2877207791","https://openalex.org/W2905212812","https://openalex.org/W2916566087","https://openalex.org/W2948850835","https://openalex.org/W2949588176","https://openalex.org/W2963082845","https://openalex.org/W2966470162","https://openalex.org/W2972614379","https://openalex.org/W3046920646","https://openalex.org/W3048414096","https://openalex.org/W3096150904","https://openalex.org/W3131733267","https://openalex.org/W3139785732","https://openalex.org/W3149617492","https://openalex.org/W3154788416","https://openalex.org/W3195784889","https://openalex.org/W3216738893","https://openalex.org/W4229786707","https://openalex.org/W4289822947","https://openalex.org/W4293519103","https://openalex.org/W4295791072","https://openalex.org/W4296704807","https://openalex.org/W4300833482","https://openalex.org/W4310732148","https://openalex.org/W4319865988","https://openalex.org/W4367721881","https://openalex.org/W4383337768","https://openalex.org/W4386557894","https://openalex.org/W4387831750","https://openalex.org/W4400966160","https://openalex.org/W4403976943","https://openalex.org/W6669791407"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2516396101","https://openalex.org/W2790557758","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W2015457513","https://openalex.org/W2013839957","https://openalex.org/W3196607417"],"abstract_inverted_index":{"In-memory":[0],"computing":[1,17,20,60],"has":[2],"been":[3],"a":[4,16,167,174],"prominent":[5],"solution":[6],"to":[7,24,43,75,111,152,165],"Von":[8],"Neumann":[9],"bottleneck":[10],"that":[11,33],"degrades":[12],"the":[13,26,39,55,70,112,119,126,137,153,160],"performance":[14,27,150],"of":[15,28,57,118,134,159,170],"system.":[18],"Approximate":[19,36],"is":[21,122,163],"widely":[22],"used":[23,42],"improve":[25],"multimedia":[29],"and":[30,61,78,104],"other":[31,45],"applications":[32],"are":[34,141],"error-tolerant.":[35],"adders":[37,140,162],"being":[38],"basic":[40],"units":[41],"design":[44],"complex":[46],"units,":[47],"get":[48],"benefited":[49],"when":[50,109],"implemented":[51,142],"in-memory":[52,59,143,155],"by":[53,82],"taking":[54],"advantages":[56],"both":[58],"approximate":[62,114,139,156],"computing.":[63],"In":[64],"this":[65],"work,":[66],"we":[67],"have":[68],"improved":[69,93],"speculative":[71],"carry":[72],"select":[73],"adder":[74,87,121,130,171],"minimize":[76],"error":[77,94,98,102,107],"critical":[79,90],"path":[80],"delay":[81],"eliminating":[83],"multiplexers.":[84],"The":[85],"proposed":[86,120,138,161],"achieves":[88],"less":[89,124],"path,":[91],"area,":[92],"characteristics":[95],"such":[96],"as":[97],"rate,":[99],"normalized":[100],"mean":[101,105],"distance":[103,108],"relative":[106],"compared":[110,151],"state-of-the-art":[113],"adders.":[115,157],"Error":[116],"rate":[117],"34.48%":[123],"than":[125],"best":[127],"reported":[128],"32-bit":[129],"with":[131],"sub-adder":[132,176],"size":[133,172],"8-bit.":[135],"When":[136],"using":[144],"majority":[145],"logic,":[146],"they":[147],"achieve":[148],"better":[149],"existing":[154],"Latency":[158],"observed":[164],"be":[166],"constant":[168],"irrespective":[169],"for":[173],"fixed":[175],"size.":[177]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}