{"id":"https://openalex.org/W4405598767","doi":"https://doi.org/10.1109/tcsi.2024.3511383","title":"FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders","display_name":"FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders","publication_year":2024,"publication_date":"2024-12-19","ids":{"openalex":"https://openalex.org/W4405598767","doi":"https://doi.org/10.1109/tcsi.2024.3511383"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3511383","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3511383","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041755258","display_name":"Morgana Macedo Azevedo da Rosa","orcid":"https://orcid.org/0000-0001-9582-9011"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Morgana Macedo Azevedo da Rosa","raw_affiliation_strings":["Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5093697235","display_name":"Leonardo Antonietti","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leonardo Antonietti","raw_affiliation_strings":["Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113091704","display_name":"Rodrigo Lopes","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Rodrigo Lopes","raw_affiliation_strings":["Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070663280","display_name":"Eloisa Barros","orcid":null},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Eloisa Barros","raw_affiliation_strings":["Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074598853","display_name":"Eduardo Costa","orcid":"https://orcid.org/0009-0009-2731-8864"},"institutions":[{"id":"https://openalex.org/I110676245","display_name":"Universidade Cat\u00f3lica de Pelotas","ror":"https://ror.org/0376myh60","country_code":"BR","type":"education","lineage":["https://openalex.org/I110676245"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Eduardo Antonio Ce\u015bar da Costa","raw_affiliation_strings":["Department of Graduate Program on Electronic Engineering and Computing, Universidade Cat&#x00F3;lica de Pelotas (UCPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Electronic Engineering and Computing, Universidade Cat&#x00F3;lica de Pelotas (UCPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I110676245"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5030974893","display_name":"Rafael Soares","orcid":"https://orcid.org/0000-0001-9493-7272"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Rafael Soares","raw_affiliation_strings":["Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Graduate Program on Computing, Universidade Federal de Pelotas (UFPel), Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5041755258"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.8302,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.74298565,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":99},"biblio":{"volume":"72","issue":"4","first_page":"1679","last_page":"1692"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7095253467559814},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5417852997779846},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48935264348983765},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4876352846622467},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4352436363697052},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.4149882197380066},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3569600582122803},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.35658910870552063},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3288901448249817},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15915194153785706},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.12718990445137024}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7095253467559814},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5417852997779846},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48935264348983765},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4876352846622467},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4352436363697052},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.4149882197380066},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3569600582122803},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.35658910870552063},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3288901448249817},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15915194153785706},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.12718990445137024}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3511383","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3511383","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321091","display_name":"Coordena\u00e7\u00e3o de Aperfei\u00e7oamento de Pessoal de N\u00edvel Superior","ror":"https://ror.org/00x0ma614"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":40,"referenced_works":["https://openalex.org/W1496057122","https://openalex.org/W1529030532","https://openalex.org/W2005865544","https://openalex.org/W2035378788","https://openalex.org/W2045294186","https://openalex.org/W2126044301","https://openalex.org/W2135089667","https://openalex.org/W2510531184","https://openalex.org/W2515531880","https://openalex.org/W2786848727","https://openalex.org/W2801205959","https://openalex.org/W2884983013","https://openalex.org/W2919795555","https://openalex.org/W2979925167","https://openalex.org/W2982216783","https://openalex.org/W2982544492","https://openalex.org/W3011299928","https://openalex.org/W3011748007","https://openalex.org/W3018203643","https://openalex.org/W3040981457","https://openalex.org/W3043004183","https://openalex.org/W3112844319","https://openalex.org/W3113701189","https://openalex.org/W3116186505","https://openalex.org/W3126588643","https://openalex.org/W3139785732","https://openalex.org/W3166637233","https://openalex.org/W3170185925","https://openalex.org/W3206051240","https://openalex.org/W4210298702","https://openalex.org/W4234974086","https://openalex.org/W4311310499","https://openalex.org/W4312283412","https://openalex.org/W4313250823","https://openalex.org/W4319069061","https://openalex.org/W4323644126","https://openalex.org/W4377969787","https://openalex.org/W4388853572","https://openalex.org/W4390187404","https://openalex.org/W4390693364"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2614722573","https://openalex.org/W2121963733","https://openalex.org/W2789349722","https://openalex.org/W1977171228","https://openalex.org/W2102927888","https://openalex.org/W4249951793","https://openalex.org/W2056896932","https://openalex.org/W2170504327"],"abstract_inverted_index":{"This":[0],"work":[1,131],"proposes":[2],"an":[3],"integrated":[4],"framework":[5,23],"for":[6,37,58,91,191,219,239,258],"accuracy":[7,171],"and":[8,21,30,42,56,66,94,104,113,119,154,167,178,214,253],"logic":[9],"synthesis":[10],"(LS)":[11],"estimation":[12],"of":[13,32,45,123,135],"approximate":[14,34],"adders":[15,35,208],"(FALSAx).":[16],"It":[17],"represents":[18],"a":[19,127],"versatile":[20],"robust":[22],"designed":[24],"to":[25,72],"estimate":[26],"the":[27,120,124,187,204],"accuracy,":[28],"power,":[29,109,112],"area":[31],"various":[33],"(AxAs)":[36],"any":[38],"input":[39],"width":[40],"(W)":[41],"K":[43],"bits":[44,194,222,242,260],"approximation":[46,193,221,241],"using":[47],"machine":[48],"learning":[49],"(ML)":[50],"models.":[51],"FALSAx":[52,97,161],"facilitates":[53],"performance":[54],"predictions":[55],"optimization":[57],"different":[59],"AxAs":[60,136],"configurations":[61],"through":[62],"meticulously":[63],"curated":[64],"datasets":[65],"ML-driven":[67],"analysis.":[68],"The":[69,96,156],"framework\u2019s":[70],"capability":[71],"automatically":[73],"generate":[74],"Pareto":[75],"fronts":[76],"from":[77],"estimated":[78],"values":[79],"aids":[80],"in":[81],"identifying":[82],"optimal":[83],"trade-offs":[84],"among":[85],"crucial":[86],"metrics,":[87],"providing":[88],"essential":[89],"insights":[90],"circuit":[92],"design":[93],"optimization.":[95],"includes":[98],"four":[99],"internal":[100],"frameworks:":[101],"FrAQ,":[102],"PILSE,":[103],"FELSE,":[105],"which":[106],"estimates":[107],"dynamic":[108],"total":[110],"leakage":[111],"area,":[114],"with":[115],"frequency":[116],"variations":[117],"automatically,":[118],"FALED":[121],"dataset":[122],"FALSAx.":[125],"As":[126],"case":[128],"study,":[129],"this":[130],"analyzed":[132],"16":[133],"types":[134],"on":[137],"FALSAx:":[138],"AMA-V,":[139,212],"AxPPA,":[140],"COPY,":[141,210],"TRUNC,":[142,211],"ETA,":[143],"LOA,":[144],"HOERAA,":[145],"LDCA,":[146,213],"LZTA,":[147],"HEAA,":[148],"M-HEAA,":[149,166],"HERLOA,":[150,164],"M-HERLOA,":[151,165],"HOAANED,":[152],"OLOCA,":[153],"SETA.":[155],"rigorous":[157],"analysis":[158,182],"provided":[159],"by":[160],"revealed":[162],"that":[163,184,234],"AxPPA":[168,185,235],"demonstrated":[169],"superior":[170],"metrics":[172],"such":[173],"as":[174],"SSIM,":[175],"NCC,":[176],"MAE,":[177],"MRE.":[179],"Furthermore,":[180],"power":[181,189],"showed":[183],"exhibited":[186],"best":[188],"efficiency":[190,238],"lower":[192,240],"(<inline-formula":[195,223,243,261],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[196,224,244,262],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[197,225,245,263],"<tex-math":[198,226,246,264],"notation=\"LaTeX\">$K":[199,227,247,265],"\\leq":[200,248],"3$":[201,229],"</tex-math></inline-formula>).":[202,230,268],"At":[203],"same":[205],"time,":[206],"gate-free":[207],"like":[209],"LZTA":[215],"were":[216,255],"more":[217,256],"power-efficient":[218],"higher":[220,259],"\\gt":[228,266],"Area":[231],"estimations":[232],"indicated":[233],"maintained":[236],"competitive":[237],"5$":[249,267],"</tex-math></inline-formula>),":[250],"while":[251],"TRUNC":[252],"LDCA":[254],"efficient":[257]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2}],"updated_date":"2026-04-02T15:55:50.835912","created_date":"2025-10-10T00:00:00"}
