{"id":"https://openalex.org/W4405179051","doi":"https://doi.org/10.1109/tcsi.2024.3507932","title":"A Half-Schmitt Trigger-Based 9T1R Nonvolatile Robust SRAM Cell for Instant On-Off Application","display_name":"A Half-Schmitt Trigger-Based 9T1R Nonvolatile Robust SRAM Cell for Instant On-Off Application","publication_year":2024,"publication_date":"2024-12-09","ids":{"openalex":"https://openalex.org/W4405179051","doi":"https://doi.org/10.1109/tcsi.2024.3507932"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3507932","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3507932","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083999738","display_name":"Mohammad Mudakir Fazili","orcid":"https://orcid.org/0000-0001-5823-3710"},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mohammad Mudakir Fazili","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Srinagar, Srinagar, Jammu and Kashmir, India"],"raw_orcid":"https://orcid.org/0000-0001-5823-3710","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Srinagar, Srinagar, Jammu and Kashmir, India","institution_ids":["https://openalex.org/I8778637"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Sayeed Ahmad","orcid":"https://orcid.org/0000-0002-5573-0321"},"institutions":[{"id":"https://openalex.org/I8778637","display_name":"National Institute of Technology Srinagar","ror":"https://ror.org/03sfwvw54","country_code":"IN","type":"education","lineage":["https://openalex.org/I4210152752","https://openalex.org/I8778637"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sayeed Ahmad","raw_affiliation_strings":["Department of Electronics and Communication Engineering, National Institute of Technology Srinagar, Srinagar, Jammu and Kashmir, India"],"raw_orcid":"https://orcid.org/0000-0002-5573-0321","affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, National Institute of Technology Srinagar, Srinagar, Jammu and Kashmir, India","institution_ids":["https://openalex.org/I8778637"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062852976","display_name":"Belal Iqbal","orcid":"https://orcid.org/0000-0001-7277-8514"},"institutions":[{"id":"https://openalex.org/I119939252","display_name":"Indraprastha Institute of Information Technology Delhi","ror":"https://ror.org/03vfp4g33","country_code":"IN","type":"education","lineage":["https://openalex.org/I119939252"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Belal Iqbal","raw_affiliation_strings":["Department of Electronics and Communication Engineering, Indraprastha Institute of Information Technology Delhi, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics and Communication Engineering, Indraprastha Institute of Information Technology Delhi, New Delhi, India","institution_ids":["https://openalex.org/I119939252"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2495,"currency":"USD","value_usd":2495},"apc_paid":null,"fwci":1.2501,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.81017039,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"72","issue":"1","first_page":"169","last_page":"179"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schmitt-trigger","display_name":"Schmitt trigger","score":0.9136321544647217},{"id":"https://openalex.org/keywords/instant","display_name":"Instant","score":0.846627950668335},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5886383652687073},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5152280926704407},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4485456347465515},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41821280121803284},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4008544981479645},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2775225043296814},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22559097409248352},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.15820369124412537},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.14160427451133728}],"concepts":[{"id":"https://openalex.org/C90201813","wikidata":"https://www.wikidata.org/wiki/Q202957","display_name":"Schmitt trigger","level":3,"score":0.9136321544647217},{"id":"https://openalex.org/C2779432360","wikidata":"https://www.wikidata.org/wiki/Q16963779","display_name":"Instant","level":2,"score":0.846627950668335},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5886383652687073},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5152280926704407},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4485456347465515},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41821280121803284},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4008544981479645},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2775225043296814},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22559097409248352},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.15820369124412537},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.14160427451133728},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3507932","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3507932","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6800000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W1506538299","https://openalex.org/W1540755418","https://openalex.org/W1971000062","https://openalex.org/W1973839642","https://openalex.org/W1979144836","https://openalex.org/W2000319719","https://openalex.org/W2004369723","https://openalex.org/W2004823737","https://openalex.org/W2007300900","https://openalex.org/W2018111008","https://openalex.org/W2021797032","https://openalex.org/W2023073815","https://openalex.org/W2024599247","https://openalex.org/W2038873698","https://openalex.org/W2045904683","https://openalex.org/W2069345435","https://openalex.org/W2099911327","https://openalex.org/W2114156831","https://openalex.org/W2140998568","https://openalex.org/W2162651880","https://openalex.org/W2213533158","https://openalex.org/W2329040051","https://openalex.org/W2433248078","https://openalex.org/W2563244511","https://openalex.org/W2699417047","https://openalex.org/W2775162082","https://openalex.org/W2804691385","https://openalex.org/W2921812058","https://openalex.org/W2934968350","https://openalex.org/W3008387290","https://openalex.org/W3119873005","https://openalex.org/W3155456425","https://openalex.org/W4221041985","https://openalex.org/W4240239951","https://openalex.org/W4283381856","https://openalex.org/W4313476484","https://openalex.org/W4320712812","https://openalex.org/W4387717663"],"related_works":["https://openalex.org/W2241423040","https://openalex.org/W2067168777","https://openalex.org/W2133555155","https://openalex.org/W2112776829","https://openalex.org/W2185746178","https://openalex.org/W3005829910","https://openalex.org/W2183474044","https://openalex.org/W2004965314","https://openalex.org/W3197002915","https://openalex.org/W4312554941"],"abstract_inverted_index":{"This":[0],"article":[1],"proposes":[2],"a":[3,67,92,201],"novel":[4],"design":[5,127,135],"of":[6,125,130,158,170,190],"9T1R":[7],"nonvolatile":[8],"static":[9,25,50],"random":[10,55],"access":[11,56,218],"memory":[12,57],"(nvSRAM).":[13],"The":[14,70,88,115,133],"proposed":[15,134,186],"nvSRAM":[16,172,192,203],"cell":[17,173,187],"significantly":[18],"improves":[19],"critical":[20],"performance":[21],"metrics":[22],"such":[23],"as":[24,141],"noise":[26,51],"margin,":[27],"read-delay,":[28],"break-even":[29],"time":[30],"(BET),":[31],"and":[32,47,75,80,103,207,216],"store/restore":[33,64,213],"delay/energy.":[34],"Schmitt":[35],"trigger":[36],"action":[37],"is":[38,60,147,174,182],"enabled":[39],"during":[40],"read":[41,44,49],"to":[42,63,83,112,143],"mitigate":[43],"disturb":[45],"problem":[46],"improve":[48],"margin.":[52],"A":[53,155],"resistive":[54],"(RRAM)":[58],"device":[59],"used":[61],"intelligently":[62],"data":[65],"in":[66,128,195],"single":[68],"cycle.":[69],"technique":[71],"reduces":[72],"the":[73,123,126,185,191],"store":[74],"restore":[76],"delay":[77,166,214],"by":[78],"50%":[79],"25%":[81],"compared":[82,111,142],"its":[84,221],"nearest":[85],"competitor":[86],"nvSRAM.":[87],"Monte-Carlo":[89],"simulations":[90,199],"demonstrate":[91,211],"very":[93],"reliable":[94],"read/write":[95],"operation":[96],"with":[97],"lower":[98],"variability":[99],"($\\sigma":[100],"/\\mu":[101],"$)":[102,110],"improved":[104],"effective":[105],"mean":[106],"($\\mu":[107],"-":[108],"3\\sigma":[109],"existing":[113,153],"nvSRAMs.":[114,154],"Worst-case":[116],"corner":[117],"analysis":[118],"under":[119],"extreme":[120],"temperatures":[121],"confirms":[122],"robustness":[124],"face":[129],"PVT":[131],"variations.":[132],"incurs":[136],"only":[137],"40%":[138],"area":[139],"overhead":[140],"6T":[144],"cell,":[145],"which":[146],"much":[148],"smaller":[149],"than":[150],"several":[151],"other":[152],"new":[156],"figure":[157],"merit":[159],"that":[160,184],"comprehensively":[161],"captures":[162],"cell-stability,":[163],"write-ability,":[164],"read/write/store/restore":[165],"&":[167],"power":[168],"dissipation":[169],"an":[171],"also":[175],"proposed.":[176],"Based":[177],"on":[178],"this":[179,196],"metric,":[180],"it":[181],"observed":[183],"outperforms":[188],"all":[189],"cells":[193],"considered":[194],"work.":[197],"Array":[198],"for":[200,223],"1Mb":[202],"at":[204],"both":[205],"typical":[206],"slow":[208],"process":[209],"corners":[210],"minimal":[212],"overheads":[215],"favorable":[217],"times,":[219],"supporting":[220],"suitability":[222],"applications":[224],"requiring":[225],"instant":[226],"on-off":[227],"functionality.":[228]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":2}],"updated_date":"2026-08-28T12:50:07.497085","created_date":"2025-10-10T00:00:00"}