{"id":"https://openalex.org/W4404520182","doi":"https://doi.org/10.1109/tcsi.2024.3497187","title":"GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow","display_name":"GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow","publication_year":2024,"publication_date":"2024-11-19","ids":{"openalex":"https://openalex.org/W4404520182","doi":"https://doi.org/10.1109/tcsi.2024.3497187"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3497187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3497187","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5014068742","display_name":"Yi Zhan","orcid":"https://orcid.org/0000-0002-6357-8091"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Yi Zhan","raw_affiliation_strings":["Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-6357-8091","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090222712","display_name":"Wei-Han Yu","orcid":"https://orcid.org/0000-0002-9079-5227"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Wei-Han Yu","raw_affiliation_strings":["Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-9079-5227","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038010873","display_name":"Ka-Fai Un","orcid":"https://orcid.org/0000-0002-7574-4755"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Ka-Fai Un","raw_affiliation_strings":["Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-7574-4755","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-3579-8740","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]},{"raw_affiliation_string":"the Faculty of Science and Technology, and the Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, the Institute of Microelectronics, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.6455,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.9136389,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"72","issue":"4","first_page":"1657","last_page":"1667"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9878000020980835,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9878000020980835,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.8377718329429626},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7428536415100098},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6832407712936401},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6717855930328369},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5820400714874268},{"id":"https://openalex.org/keywords/transformer","display_name":"Transformer","score":0.508470892906189},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4575080871582031},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39584076404571533},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3818001449108124},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37849050760269165},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2675752341747284},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21020767092704773},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15206298232078552},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07323747873306274}],"concepts":[{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.8377718329429626},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7428536415100098},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6832407712936401},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6717855930328369},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5820400714874268},{"id":"https://openalex.org/C66322947","wikidata":"https://www.wikidata.org/wiki/Q11658","display_name":"Transformer","level":3,"score":0.508470892906189},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4575080871582031},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39584076404571533},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3818001449108124},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37849050760269165},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2675752341747284},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21020767092704773},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15206298232078552},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07323747873306274},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3497187","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3497187","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G489093131","display_name":null,"funder_award_id":"0040/2024/AGJ","funder_id":"https://openalex.org/F4320315893","funder_display_name":"VNU Science and Technology Development Fund"},{"id":"https://openalex.org/G6548532224","display_name":null,"funder_award_id":"004/2023/SKL","funder_id":"https://openalex.org/F4320315893","funder_display_name":"VNU Science and Technology Development Fund"},{"id":"https://openalex.org/G8111037719","display_name":null,"funder_award_id":"2220004002683","funder_id":"https://openalex.org/F4320336584","funder_display_name":"Dalian Science and Technology Innovation Fund"},{"id":"https://openalex.org/G832237197","display_name":null,"funder_award_id":"0136/2024/AMJ","funder_id":"https://openalex.org/F4320315893","funder_display_name":"VNU Science and Technology Development Fund"}],"funders":[{"id":"https://openalex.org/F4320315893","display_name":"VNU Science and Technology Development Fund","ror":"https://ror.org/044vr6g03"},{"id":"https://openalex.org/F4320336584","display_name":"Dalian Science and Technology Innovation Fund","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W2067523571","https://openalex.org/W2289252105","https://openalex.org/W2604319603","https://openalex.org/W2625457103","https://openalex.org/W3017521908","https://openalex.org/W3020759376","https://openalex.org/W3099871312","https://openalex.org/W3139521791","https://openalex.org/W3168649818","https://openalex.org/W3208788005","https://openalex.org/W3211525823","https://openalex.org/W4220686330","https://openalex.org/W4225364593","https://openalex.org/W4226353746","https://openalex.org/W4285309026","https://openalex.org/W4312847929","https://openalex.org/W4313467238","https://openalex.org/W4313839325","https://openalex.org/W4313887270","https://openalex.org/W4360605374","https://openalex.org/W4360605490","https://openalex.org/W4360606196","https://openalex.org/W4360607288","https://openalex.org/W4382203417","https://openalex.org/W4383501624","https://openalex.org/W4385080060","https://openalex.org/W4387129467","https://openalex.org/W4387490588","https://openalex.org/W4388109028","https://openalex.org/W4388469893","https://openalex.org/W4390097310","https://openalex.org/W4390776943","https://openalex.org/W4391892592","https://openalex.org/W4392745569","https://openalex.org/W4392746193","https://openalex.org/W4394966876","https://openalex.org/W6857972656","https://openalex.org/W6870125966"],"related_works":["https://openalex.org/W2293118914","https://openalex.org/W2998381397","https://openalex.org/W4236419692","https://openalex.org/W2171015181","https://openalex.org/W3167919718","https://openalex.org/W4251718783","https://openalex.org/W4239447582","https://openalex.org/W1484403103","https://openalex.org/W2521947294","https://openalex.org/W1998888015"],"abstract_inverted_index":{"This":[0],"article":[1],"reports":[2],"a":[3,34,80,124,133],"globally":[4],"systolic":[5,38],"and":[6,13,20,57,103,132,146,156,169,183],"locally":[7],"parallel":[8],"(GSLP)":[9],"convolutional":[10],"NN":[11],"(CNN)":[12],"Transformer":[14],"accelerator":[15,122],"based":[16],"on":[17],"the":[18,42,72,88,91,101,107,119,151,162,172],"scalable":[19],"reconfigurable":[21,43,66],"(SR)":[22],"embedded":[23],"dynamic":[24],"random-access":[25],"memory":[26,68],"(eDRAM)":[27],"compute-in-memory":[28],"(CIM)":[29],"macro.":[30,113],"It":[31],"features:":[32],"1)":[33],"GSLP":[35],"architecture":[36],"employs":[37],"CIM":[39,112],"macros":[40],"with":[41,144],"inter-CIM":[44],"network":[45],"to":[46,70,85,99],"support":[47],"flexible":[48],"dataflow,":[49],"including":[50],"weight":[51],"stationary":[52,55,59],"(WS),":[53],"output":[54],"(OS),":[56],"Row":[58],"(RS);":[60],"2)":[61],"an":[62,94],"SR-CIM":[63],"macro":[64],"features":[65],"weight/input/output":[67],"ratio":[69],"maximize":[71],"related":[73],"data":[74],"reuse":[75],"in":[76,110,115],"different":[77],"dataflow;":[78],"3)":[79],"high-density":[81],"3T":[82],"eDRAM-CIM":[83],"cell":[84],"further":[86],"improve":[87],"density":[89,128,165],"of":[90,106,129,139,154,166,177],"accelerator;":[92],"4)":[93],"area-efficient":[95],"in-memory":[96],"accumulator":[97],"(IMA)":[98],"save":[100],"area":[102],"power":[104],"overhead":[105],"digital":[108],"accumulation":[109],"each":[111],"Prototyped":[114],"28-nm":[116],"CMOS":[117],"process,":[118],"proposed":[120],"GSLP-CIM":[121],"exhibits":[123],"4b":[125,134],"peak":[126,135],"throughput":[127,153,164],"0.16":[130],"TOPS/mm2":[131],"compute":[136,174],"energy":[137,175],"efficiency":[138,176],"3.55":[140],"TOPS/W.":[141],"Specifically,":[142],"evaluated":[143],"ResNet-50@ImageNet":[145],"ViT-B@ImageNet,":[147],"this":[148],"work":[149],"reaches":[150],"system":[152,163,173],"24.5":[155],"5.66":[157],"inferences":[158,179],"per":[159,180],"second":[160],"(IPS),":[161],"19.3":[167],"IPS/mm2":[168],"4.46":[170],"IPS/mm2,":[171],"423.9":[178],"watt":[181],"(IPW)":[182],"97.6":[184],"IPW,":[185],"respectively.":[186]},"counts_by_year":[{"year":2026,"cited_by_count":2},{"year":2025,"cited_by_count":6}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
