{"id":"https://openalex.org/W4402742364","doi":"https://doi.org/10.1109/tcsi.2024.3458436","title":"A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme","display_name":"A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme","publication_year":2024,"publication_date":"2024-09-23","ids":{"openalex":"https://openalex.org/W4402742364","doi":"https://doi.org/10.1109/tcsi.2024.3458436"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3458436","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3458436","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102739801","display_name":"Qiqiao Wu","orcid":"https://orcid.org/0009-0005-5258-2190"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Qiqiao Wu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002489915","display_name":"Honghu Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I126520041","display_name":"University of Science and Technology of China","ror":"https://ror.org/04c4dkn09","country_code":"CN","type":"education","lineage":["https://openalex.org/I126520041","https://openalex.org/I19820366"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Honghu Yang","raw_affiliation_strings":["School of Microelectronics, University of Science and Technology of China, Hefei, China"],"affiliations":[{"raw_affiliation_string":"School of Microelectronics, University of Science and Technology of China, Hefei, China","institution_ids":["https://openalex.org/I126520041"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119507273","display_name":"Yixuan Liu","orcid":"https://orcid.org/0000-0003-3969-1833"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yixuan Liu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001376937","display_name":"Yue Cao","orcid":"https://orcid.org/0000-0001-6948-7222"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yue Cao","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062637389","display_name":"Yongkang Han","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yongkang Han","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036612716","display_name":"Haijun Jiang","orcid":"https://orcid.org/0000-0002-0310-6842"},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haijun Jiang","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085433686","display_name":"Keji Zhou","orcid":"https://orcid.org/0000-0002-3078-4542"},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Keji Zhou","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111337113","display_name":"Hailan Yi","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hailan Yi","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045358041","display_name":"Jianguo Yang","orcid":"https://orcid.org/0000-0002-3387-1238"},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianguo Yang","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"last","author":{"id":null,"display_name":"Qi Liu","orcid":"https://orcid.org/0000-0001-7062-831X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qi Liu","raw_affiliation_strings":["State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Integrated Chips and Systems, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":10,"corresponding_author_ids":["https://openalex.org/A5102739801"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2054,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.51705803,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"72","issue":"3","first_page":"1383","last_page":"1396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/neuromorphic-engineering","display_name":"Neuromorphic engineering","score":0.9212069511413574},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.7296366095542908},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.7211958765983582},{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.6115858554840088},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5610175132751465},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4959746301174164},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48814043402671814},{"id":"https://openalex.org/keywords/chain","display_name":"Chain (unit)","score":0.47716325521469116},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45006808638572693},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.42121443152427673},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3736985921859741},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2509445548057556},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.24907979369163513},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22586053609848022},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19919922947883606},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16610857844352722},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14484083652496338},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1271107792854309}],"concepts":[{"id":"https://openalex.org/C151927369","wikidata":"https://www.wikidata.org/wiki/Q1981312","display_name":"Neuromorphic engineering","level":3,"score":0.9212069511413574},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.7296366095542908},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.7211958765983582},{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.6115858554840088},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5610175132751465},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4959746301174164},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48814043402671814},{"id":"https://openalex.org/C199185054","wikidata":"https://www.wikidata.org/wiki/Q552299","display_name":"Chain (unit)","level":2,"score":0.47716325521469116},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45006808638572693},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.42121443152427673},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3736985921859741},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2509445548057556},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.24907979369163513},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22586053609848022},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19919922947883606},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16610857844352722},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14484083652496338},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1271107792854309},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3458436","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3458436","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G4133108643","display_name":null,"funder_award_id":"XDB44000000","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G417164712","display_name":null,"funder_award_id":"62025406","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6200683350","display_name":null,"funder_award_id":"92164204","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G6558924418","display_name":null,"funder_award_id":"62104040","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G8031315765","display_name":null,"funder_award_id":"62222119","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":53,"referenced_works":["https://openalex.org/W1570411240","https://openalex.org/W1604973310","https://openalex.org/W1966939297","https://openalex.org/W2004823737","https://openalex.org/W2051736202","https://openalex.org/W2120676354","https://openalex.org/W2125700950","https://openalex.org/W2126241821","https://openalex.org/W2137862082","https://openalex.org/W2165093231","https://openalex.org/W2167326092","https://openalex.org/W2168972302","https://openalex.org/W2329040051","https://openalex.org/W2432549741","https://openalex.org/W2584335437","https://openalex.org/W2617220603","https://openalex.org/W2727726870","https://openalex.org/W2734294704","https://openalex.org/W2768126690","https://openalex.org/W2775079417","https://openalex.org/W2787336703","https://openalex.org/W2793181810","https://openalex.org/W2795874008","https://openalex.org/W2802694254","https://openalex.org/W2807457908","https://openalex.org/W2816513951","https://openalex.org/W2884551039","https://openalex.org/W2899441512","https://openalex.org/W2964338223","https://openalex.org/W3037965865","https://openalex.org/W3048446883","https://openalex.org/W3118927099","https://openalex.org/W3127180651","https://openalex.org/W3134756900","https://openalex.org/W3150929849","https://openalex.org/W3155837802","https://openalex.org/W3164529716","https://openalex.org/W3180917267","https://openalex.org/W3192817241","https://openalex.org/W3203407933","https://openalex.org/W3209682179","https://openalex.org/W4200539568","https://openalex.org/W4200611376","https://openalex.org/W4210903307","https://openalex.org/W4213414822","https://openalex.org/W4225295764","https://openalex.org/W4288068957","https://openalex.org/W4292121737","https://openalex.org/W4389459350","https://openalex.org/W4392745539","https://openalex.org/W4395680546","https://openalex.org/W6638947222","https://openalex.org/W6760981999"],"related_works":["https://openalex.org/W1872623660","https://openalex.org/W4292697011","https://openalex.org/W3207218810","https://openalex.org/W3212508523","https://openalex.org/W1995352804","https://openalex.org/W2909534142","https://openalex.org/W2793181810","https://openalex.org/W4367187682","https://openalex.org/W2891417865","https://openalex.org/W4386475142"],"abstract_inverted_index":{"The":[0,66,140],"neuromorphic":[1,46,52],"system":[2],"aims":[3],"to":[4,28,40,84,115,172,190],"implement":[5],"large-scale":[6],"spiking":[7],"neural":[8],"networks":[9],"(SNN)":[10],"through":[11],"hardware,":[12],"ultimately":[13],"achieving":[14],"human-level":[15],"intelligence.":[16],"At":[17],"this":[18],"stage,":[19],"it":[20,37],"is":[21,38,170,188],"difficult":[22],"for":[23,104],"a":[24,50,72,93,98],"single":[25],"silicon-based":[26],"chip":[27],"reach":[29],"the":[30,33,42,85,89,105,113,121,134,164,167,183],"density":[31],"of":[32,45,76,112,124,136,148,155,185],"human":[34],"brain,":[35],"so":[36],"important":[39],"improve":[41],"area":[43,95,154],"efficiency":[44],"chips.":[47],"We":[48],"present":[49],"novel":[51],"hardware":[53],"that":[54,132],"employs":[55],"high":[56],"area-efficiency":[57],"chain":[58,68,90],"RRAM":[59,69,110,187],"synaptic":[60],"array,":[61],"and":[62,97,152,182],"compact":[63],"RRAM-based":[64],"neurons.":[65],"proposed":[67],"structure":[70,91],"achieves":[71],"small":[73],"cell":[74],"size":[75],"41.5F2":[77],"at":[78],"28":[79],"nm":[80],"logic":[81],"process.":[82],"Compared":[83],"conventional":[86],"1T1R":[87],"structure,":[88],"has":[92],"22.2%":[94],"reduction":[96],"58.8%":[99],"parasitic":[100],"capacitance":[101],"reduction.":[102],"As":[103],"neuron":[106],"design,":[107],"we":[108,126],"use":[109],"instead":[111],"capacitor":[114],"integrate":[116],"membrane":[117,137],"voltage.":[118],"To":[119],"alleviate":[120],"endurance":[122],"issue":[123],"RRAM,":[125],"propose":[127],"an":[128,144,153],"(anti-)":[129],"integration":[130],"scheme":[131],"removes":[133],"operation":[135],"voltage":[138],"reset.":[139],"simulation":[141],"results":[142],"demonstrate":[143],"average":[145],"energy":[146,184],"consumption":[147],"1.15pJ":[149],"per":[150],"spike":[151],"<inline-formula":[156,175,194],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[157,176,195],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[158,177,196],"<tex-math":[159,178,197],"notation=\"LaTeX\">$15.9\\mu":[160],"$":[161,180,199],"</tex-math></inline-formula>m2.":[162],"With":[163],"(anti-)integration":[165],"scheme,":[166],"RRAM\u2019s":[168],"lifetime":[169],"demonstrated":[171,189],"extend":[173],"by":[174,193],"notation=\"LaTeX\">$2\\times":[179,198],"</tex-math></inline-formula>":[181],"programming":[186],"be":[191],"reduced":[192],"</tex-math></inline-formula>.":[200]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-04-09T08:11:56.329763","created_date":"2025-10-10T00:00:00"}