{"id":"https://openalex.org/W4400187883","doi":"https://doi.org/10.1109/tcsi.2024.3416204","title":"Hardware-Efficient Multipliers With FPGA-Based Approximation for Error-Resilient Applications","display_name":"Hardware-Efficient Multipliers With FPGA-Based Approximation for Error-Resilient Applications","publication_year":2024,"publication_date":"2024-07-01","ids":{"openalex":"https://openalex.org/W4400187883","doi":"https://doi.org/10.1109/tcsi.2024.3416204"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3416204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3416204","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087319413","display_name":"Yi Guo","orcid":"https://orcid.org/0009-0007-4639-1413"},"institutions":[{"id":"https://openalex.org/I189210763","display_name":"Yunnan University","ror":"https://ror.org/0040axw97","country_code":"CN","type":"education","lineage":["https://openalex.org/I189210763"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Yi Guo","raw_affiliation_strings":["Graduate School of Information, Science and Engineering and Yunnan Key Laboratory of Intelligent Systems and Computing, Yunnan University, Kunming, China"],"raw_orcid":"https://orcid.org/0009-0007-4639-1413","affiliations":[{"raw_affiliation_string":"Graduate School of Information, Science and Engineering and Yunnan Key Laboratory of Intelligent Systems and Computing, Yunnan University, Kunming, China","institution_ids":["https://openalex.org/I189210763"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075038156","display_name":"Qi\u2010Lin Zhou","orcid":"https://orcid.org/0000-0002-4700-3765"},"institutions":[{"id":"https://openalex.org/I189210763","display_name":"Yunnan University","ror":"https://ror.org/0040axw97","country_code":"CN","type":"education","lineage":["https://openalex.org/I189210763"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qilin Zhou","raw_affiliation_strings":["Graduate School of Information, Science and Engineering, Yunnan University, Kunming, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Science and Engineering, Yunnan University, Kunming, China","institution_ids":["https://openalex.org/I189210763"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020376217","display_name":"Xiu Chen","orcid":"https://orcid.org/0000-0001-9227-6298"},"institutions":[{"id":"https://openalex.org/I189210763","display_name":"Yunnan University","ror":"https://ror.org/0040axw97","country_code":"CN","type":"education","lineage":["https://openalex.org/I189210763"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiu Chen","raw_affiliation_strings":["Graduate School of Information, Science and Engineering, Yunnan University, Kunming, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Science and Engineering, Yunnan University, Kunming, China","institution_ids":["https://openalex.org/I189210763"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089205282","display_name":"Heming Sun","orcid":"https://orcid.org/0000-0001-5583-4895"},"institutions":[{"id":"https://openalex.org/I180203408","display_name":"Yokohama National University","ror":"https://ror.org/03zyp6p76","country_code":"JP","type":"education","lineage":["https://openalex.org/I180203408"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Heming Sun","raw_affiliation_strings":["Faculty of Engineering, Yokohama National University, Yokohama, Kanagawa, Japan"],"raw_orcid":"https://orcid.org/0000-0001-5583-4895","affiliations":[{"raw_affiliation_string":"Faculty of Engineering, Yokohama National University, Yokohama, Kanagawa, Japan","institution_ids":["https://openalex.org/I180203408"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5087319413"],"corresponding_institution_ids":["https://openalex.org/I189210763"],"apc_list":null,"apc_paid":null,"fwci":3.0043,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.91685109,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":"71","issue":"12","first_page":"5919","last_page":"5930"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9937000274658203,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6562401652336121},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6326805353164673},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4423379600048065},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41876423358917236},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4072645902633667},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3616315722465515},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1911955177783966}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6562401652336121},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6326805353164673},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4423379600048065},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41876423358917236},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4072645902633667},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3616315722465515},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1911955177783966}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3416204","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3416204","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G1161857703","display_name":null,"funder_award_id":"202405AV340009","funder_id":"https://openalex.org/F4320327808","funder_display_name":"Yunnan Key Research and Development Program"}],"funders":[{"id":"https://openalex.org/F4320327808","display_name":"Yunnan Key Research and Development Program","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W1988918651","https://openalex.org/W1998824039","https://openalex.org/W2086709052","https://openalex.org/W2124651102","https://openalex.org/W2133665775","https://openalex.org/W2612139336","https://openalex.org/W2808327285","https://openalex.org/W2946711010","https://openalex.org/W2948850835","https://openalex.org/W2963082845","https://openalex.org/W3004524066","https://openalex.org/W3013744920","https://openalex.org/W3018565930","https://openalex.org/W3036553373","https://openalex.org/W3037251238","https://openalex.org/W3048414096","https://openalex.org/W3126267573","https://openalex.org/W3135997061","https://openalex.org/W4239085833","https://openalex.org/W4255177036","https://openalex.org/W4311839916","https://openalex.org/W4319878806","https://openalex.org/W4327662570","https://openalex.org/W4386557894"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4200391368","https://openalex.org/W2355315220","https://openalex.org/W2210979487","https://openalex.org/W2074043759","https://openalex.org/W2316202402","https://openalex.org/W2373535795","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"Approximate":[0],"multipliers":[1,12,48,108,123,138,194,234,255,276],"enable":[2],"hardware":[3,250],"savings":[4],"for":[5,27,77,145],"error-resilient":[6],"computation-intensive":[7],"applications.":[8],"Most":[9],"existing":[10],"approximate":[11,39,98,150,185,254],"have":[13],"been":[14],"on":[15,258],"ASIC-based":[16],"circuits.":[17],"They":[18],"might":[19],"not":[20],"achieve":[21,161],"comparable":[22],"performance":[23,214],"gains":[24],"when":[25],"used":[26],"FPGA-based":[28,36],"accelerators.":[29],"In":[30],"this":[31],"paper,":[32],"we":[33],"propose":[34],"hardware-efficient":[35],"accurate":[37,183],"and":[38,57,139,166,172,184,284,289],"<inline-formula":[40,115,130,151,186,201,217],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[41,116,131,152,187,202,218,282],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[42,117,132,153,188,203,219],"<tex-math":[43,118,133,154,189,204,220],"notation=\"LaTeX\">$4\\boldsymbol":[44,134],"{\\times":[45,120,135,156,191,206,222],"}4$":[46,136],"</tex-math></inline-formula>":[47,122,137,158,193,208,224],"with":[49,71,109,195,237],"novel":[50],"methodologies":[51],"of":[52,106,114,215,261,273],"look-up":[53],"table":[54],"(LUT)":[55],"sharing":[56,68],"carry":[58,83],"switching.":[59],"The":[60,148],"LUT":[61],"resources":[62],"can":[63,160],"be":[64],"fully":[65],"utilized":[66],"by":[67,87,126,212],"two":[69],"LUTs":[70],"the":[72,78,81,91,104,107,128,175,181,213,216,229,245,253,259,266,274],"same":[73],"inputs.":[74],"To":[75],"compensate":[76],"accuracy":[79,243],"loss,":[80,244],"truncated":[82],"is":[84,278],"partially":[85],"reserved":[86],"switching":[88],"it":[89],"to":[90,102,163,200,231,264],"adjacent":[92],"calculation.":[93],"For":[94],"higher-order":[95,233],"multipliers,":[96,225],"three":[97],"adders":[99,197],"are":[100,124,198,256],"proposed":[101,129,149,182,246,275],"sum":[103],"result":[105],"arbitrary":[110],"size.":[111],"140":[112],"types":[113],"notation=\"LaTeX\">$8\\boldsymbol":[119,155,190],"}8$":[121,157,192],"constructed":[125],"combining":[127],"adders,":[140],"providing":[141],"various":[142],"multiplication":[143],"choices":[144],"different":[146,196],"demands.":[147],"multiplier":[159,247],"up":[162],"38.75%,":[164],"17.29%,":[165],"28.17%":[167],"improvements":[168],"in":[169,286],"power,":[170],"latency,":[171],"area":[173],"over":[174],"Xilinx":[176],"exact":[177],"multiplier,":[178],"respectively.":[179],"Moreover,":[180],"extended":[199],"notation=\"LaTeX\">$16\\boldsymbol":[205,221],"}16$":[207,223],"multipliers.":[209],"As":[210],"evidenced":[211],"our":[226],"methodology":[227],"demonstrates":[228],"capability":[230],"design":[232],"flexibly.":[235],"Compared":[236],"previous":[238],"works":[239],"under":[240],"a":[241,271],"similar":[242],"achieves":[248],"more":[249],"savings.":[251],"Furthermore,":[252],"assessed":[257],"application":[260],"image":[262],"processing":[263],"validate":[265],"practical":[267],"applicability.":[268],"We":[269],"create":[270],"library":[272],"which":[277],"open-source":[279],"at":[280],"<uri":[281],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">https://github.com/YnuGuoLab/Approx_Mul_FPGA/</uri>":[283],"assist":[285],"further":[287],"reproducing":[288],"development.":[290]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":12}],"updated_date":"2025-12-26T23:08:49.675405","created_date":"2025-10-10T00:00:00"}