{"id":"https://openalex.org/W4399880783","doi":"https://doi.org/10.1109/tcsi.2024.3411608","title":"A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks","display_name":"A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks","publication_year":2024,"publication_date":"2024-06-21","ids":{"openalex":"https://openalex.org/W4399880783","doi":"https://doi.org/10.1109/tcsi.2024.3411608"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3411608","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3411608","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003541204","display_name":"Chengshuo Yu","orcid":"https://orcid.org/0000-0003-0897-7871"},"institutions":[{"id":"https://openalex.org/I4210114190","display_name":"Shanghai Zhangjiang Laboratory","ror":"https://ror.org/0208qbg77","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210114190"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chengshuo Yu","raw_affiliation_strings":["Zhangjiang Laboratory, Shanghai, China"],"raw_orcid":"https://orcid.org/0000-0003-0897-7871","affiliations":[{"raw_affiliation_string":"Zhangjiang Laboratory, Shanghai, China","institution_ids":["https://openalex.org/I4210114190"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5014052102","display_name":"Haoge Jiang","orcid":"https://orcid.org/0000-0001-8249-4849"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Haoge Jiang","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore"],"raw_orcid":"https://orcid.org/0000-0001-8249-4849","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011907615","display_name":"Junjie Mu","orcid":"https://orcid.org/0000-0002-6496-6539"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Junjie Mu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore"],"raw_orcid":"https://orcid.org/0000-0002-6496-6539","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065841007","display_name":"Kevin Tshun Chuan Chai","orcid":"https://orcid.org/0000-0001-6624-8912"},"institutions":[{"id":"https://openalex.org/I115228651","display_name":"Agency for Science, Technology and Research","ror":"https://ror.org/036wvzt09","country_code":"SG","type":"government","lineage":["https://openalex.org/I115228651"]},{"id":"https://openalex.org/I2799413724","display_name":"Singapore Science Park","ror":"https://ror.org/0023asr12","country_code":"SG","type":"archive","lineage":["https://openalex.org/I2799413724"]},{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Kevin Tshun Chuan Chai","raw_affiliation_strings":["Institute of Microelectronics, Agency for Science Technology and Research (A&#x002A;STAR), Singapore Science Park II, Singapore"],"raw_orcid":"https://orcid.org/0000-0001-6624-8912","affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Agency for Science Technology and Research (A&#x002A;STAR), Singapore Science Park II, Singapore","institution_ids":["https://openalex.org/I2799413724","https://openalex.org/I4210090209","https://openalex.org/I115228651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076628109","display_name":"Tony Tae-Hyoung Kim","orcid":"https://orcid.org/0000-0002-1779-1799"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Tony Tae-Hyoung Kim","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore"],"raw_orcid":"https://orcid.org/0000-0002-1779-1799","affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035469250","display_name":"Bongjin Kim","orcid":"https://orcid.org/0000-0001-5397-9628"},"institutions":[{"id":"https://openalex.org/I154570441","display_name":"University of California, Santa Barbara","ror":"https://ror.org/02t274463","country_code":"US","type":"education","lineage":["https://openalex.org/I154570441"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bongjin Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0001-5397-9628","affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA, USA","institution_ids":["https://openalex.org/I154570441"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.1137,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.77265369,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":98,"max":99},"biblio":{"volume":"71","issue":"8","first_page":"3672","last_page":"3682"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12676","display_name":"Machine Learning and ELM","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6691173911094666},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6668744087219238},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.6201111078262329},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5790738463401794},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5702334046363831},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.4971955120563507},{"id":"https://openalex.org/keywords/zero","display_name":"Zero (linguistics)","score":0.4606904983520508},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41334694623947144},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.38282665610313416},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33510348200798035},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3246151804924011},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18253010511398315},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1385602056980133}],"concepts":[{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6691173911094666},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6668744087219238},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.6201111078262329},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5790738463401794},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5702334046363831},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.4971955120563507},{"id":"https://openalex.org/C2780813799","wikidata":"https://www.wikidata.org/wiki/Q3274237","display_name":"Zero (linguistics)","level":2,"score":0.4606904983520508},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41334694623947144},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.38282665610313416},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33510348200798035},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3246151804924011},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18253010511398315},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1385602056980133},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3411608","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3411608","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":49,"referenced_works":["https://openalex.org/W1999085092","https://openalex.org/W2300242332","https://openalex.org/W2319920447","https://openalex.org/W2524428287","https://openalex.org/W2777372517","https://openalex.org/W2782511028","https://openalex.org/W2809624076","https://openalex.org/W2894696827","https://openalex.org/W2963029056","https://openalex.org/W2966285227","https://openalex.org/W2990591126","https://openalex.org/W3000301330","https://openalex.org/W3015655039","https://openalex.org/W3016014942","https://openalex.org/W3016021860","https://openalex.org/W3043783230","https://openalex.org/W3091205277","https://openalex.org/W3097655915","https://openalex.org/W3099871312","https://openalex.org/W3128966520","https://openalex.org/W3133754064","https://openalex.org/W3134526034","https://openalex.org/W3134893068","https://openalex.org/W3134925155","https://openalex.org/W3135906938","https://openalex.org/W3137147200","https://openalex.org/W3159353913","https://openalex.org/W3164913974","https://openalex.org/W3208771313","https://openalex.org/W3212381966","https://openalex.org/W4214833843","https://openalex.org/W4225739994","https://openalex.org/W4226402784","https://openalex.org/W4284991974","https://openalex.org/W4285190189","https://openalex.org/W4285820332","https://openalex.org/W4308089786","https://openalex.org/W4313644165","https://openalex.org/W4313839325","https://openalex.org/W4319459123","https://openalex.org/W4320713062","https://openalex.org/W4376134015","https://openalex.org/W4388214769","https://openalex.org/W6693397755","https://openalex.org/W6700264148","https://openalex.org/W6727208969","https://openalex.org/W6753069482","https://openalex.org/W6779885597","https://openalex.org/W6848317088"],"related_works":["https://openalex.org/W2030816003","https://openalex.org/W4239992647","https://openalex.org/W2150013480","https://openalex.org/W1554458299","https://openalex.org/W2076325756","https://openalex.org/W81423522","https://openalex.org/W1509860481","https://openalex.org/W3151633427","https://openalex.org/W2488264085","https://openalex.org/W2958550830"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,29,91,123,136,172],"novel":[4],"dual":[5,46,157],"7T":[6,47],"static":[7],"random-access":[8],"memory":[9],"(SRAM)-based":[10],"compute-in-memory":[11],"(CIM)":[12],"macro":[13,23],"for":[14,90,102,114,162,192,231,260],"processing":[15,163],"quantized":[16],"neural":[17,164],"networks.":[18],"The":[19,118,151,183,201,250],"proposed":[20],"SRAM-based":[21],"CIM":[22],"decouples":[24],"read/write":[25],"operations":[26,55],"and":[27,53,67,105,190,196,229,235,257,264],"employs":[28],"zero-input/weight":[30],"skipping":[31],"scheme.":[32],"A":[33],"65nm":[34],"test":[35,152],"chip":[36,153],"with":[37,56,154,177,212,239],"<inline-formula":[38,57,68,82,94,106],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[39,58,69,83,95,107],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[40,59,70,84,96,108],"<tex-math":[41,60,71,85,97,109],"notation=\"LaTeX\">$528\\times":[42],"128$":[43,73],"</tex-math></inline-formula>":[44,63,74,88,100,112],"integrated":[45],"bitcells":[48,89,101,113,159],"demonstrated":[49],"reconfigurable":[50],"precision":[51],"multiply":[52],"accumulate":[54],"notation=\"LaTeX\">$384\\times":[61,72,86],"$":[62,87,99,111],"binary":[64,142],"inputs":[65],"(0/1)":[66],"programmable":[75],"multi-bit":[76],"weights":[77],"(3/7/15-levels).":[78],"Each":[79],"column":[80],"comprises":[81],"dot":[92],"product,":[93],"notation=\"LaTeX\">$48\\times":[98],"offset":[103],"calibration,":[104],"notation=\"LaTeX\">$96\\times":[110],"binary-searching":[115],"analog-to-digital":[116,119],"conversion.":[117],"converter":[120],"(ADC)":[121],"converts":[122],"voltage":[124],"difference":[125],"between":[126],"two":[127],"read":[128],"bitlines":[129],"(i.e.,":[130],"an":[131],"analog":[132],"dot-product":[133],"result)":[134],"to":[135,207,244],"1-6b":[137],"digital":[138],"output":[139],"code":[140],"using":[141,148,171,219],"searching":[143],"in":[144],"1-6":[145],"conversion":[146],"cycles":[147],"replica":[149],"bitcells.":[150],"66Kb":[155],"embedded":[156],"SRAM":[158],"was":[160],"evaluated":[161],"networks,":[165],"including":[166],"the":[167,193,210,216,220,224,232,247,261],"MNIST":[168],"image":[169,222],"classifications":[170],"multi-layer":[173],"perceptron":[174],"(MLP)":[175],"model":[176,218],"its":[178],"layer":[179],"configuration":[180],"of":[181,241],"784-256-256-256-10.":[182],"measured":[184,251,269],"classification":[185],"accuracies":[186,225],"are":[187,204,226,254],"97.62%,":[188],"97.65%,":[189],"97.72%":[191],"3,":[194,233,262],"7,":[195,234,263],"15":[197,236,265],"level":[198,237,266],"weights,":[199,238,267],"respectively.":[200],"accuracy":[202],"degradations":[203,240],"only":[205,242],"0.58":[206],"0.74%":[208],"off":[209,246],"baseline":[211],"software":[213,248],"simulations.":[214],"For":[215],"VGG6":[217],"CIFAR-10":[221],"dataset,":[223],"88.59%,":[227],"88.21%,":[228],"89.07%":[230],"0.6":[243],"1.32%":[245],"baseline.":[249],"energy":[252],"efficiencies":[253],"258.5,":[255],"67.9,":[256],"23.9":[258],"TOPS/W":[259],"respectively,":[268],"at":[270],"0.45/0.8V":[271],"supplies.":[272]},"counts_by_year":[{"year":2025,"cited_by_count":6}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
