{"id":"https://openalex.org/W4391248531","doi":"https://doi.org/10.1109/tcsi.2024.3354995","title":"A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC","display_name":"A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC","publication_year":2024,"publication_date":"2024-01-26","ids":{"openalex":"https://openalex.org/W4391248531","doi":"https://doi.org/10.1109/tcsi.2024.3354995"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2024.3354995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3354995","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047256160","display_name":"Haolin Han","orcid":"https://orcid.org/0000-0003-4566-1569"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Haolin Han","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0003-4566-1569","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100635138","display_name":"Shubin Liu","orcid":"https://orcid.org/0000-0002-9942-0069"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shubin Liu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-9942-0069","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077372163","display_name":"Hongzhi Liang","orcid":"https://orcid.org/0000-0001-6609-9486"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongzhi Liang","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0001-6609-9486","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5029781634","display_name":"Yi Shen","orcid":"https://orcid.org/0000-0002-2586-3772"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yi Shen","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-2586-3772","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102116306","display_name":"Jianyu Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianyu Guo","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102634616","display_name":"Ruili Ren","orcid":null},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ruili Ren","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039575274","display_name":"Zhangming Zhu","orcid":"https://orcid.org/0000-0002-7764-1928"},"institutions":[{"id":"https://openalex.org/I149594827","display_name":"Xidian University","ror":"https://ror.org/05s92vm98","country_code":"CN","type":"education","lineage":["https://openalex.org/I149594827"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhangming Zhu","raw_affiliation_strings":["Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"],"raw_orcid":"https://orcid.org/0000-0002-7764-1928","affiliations":[{"raw_affiliation_string":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China","institution_ids":["https://openalex.org/I149594827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I149594827"],"apc_list":null,"apc_paid":null,"fwci":1.3645,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.77784866,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":98},"biblio":{"volume":"71","issue":"4","first_page":"1495","last_page":"1505"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/serialization","display_name":"Serialization","score":0.6987292766571045},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.6408154368400574},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5222761631011963},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.46065446734428406},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.4470653831958771},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37939950823783875},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3310217559337616},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.3271174728870392},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30658018589019775},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.20023953914642334},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1999075710773468},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13791197538375854}],"concepts":[{"id":"https://openalex.org/C52723943","wikidata":"https://www.wikidata.org/wiki/Q1127410","display_name":"Serialization","level":2,"score":0.6987292766571045},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.6408154368400574},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5222761631011963},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.46065446734428406},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.4470653831958771},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37939950823783875},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3310217559337616},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.3271174728870392},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30658018589019775},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.20023953914642334},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1999075710773468},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13791197538375854},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2024.3354995","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2024.3354995","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8700000047683716}],"awards":[{"id":"https://openalex.org/G1296667907","display_name":null,"funder_award_id":"62090043","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2320218852","display_name":null,"funder_award_id":"62021004","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"},{"id":"https://openalex.org/G2351528596","display_name":null,"funder_award_id":"62227816","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1970809947","https://openalex.org/W2107763413","https://openalex.org/W2108324407","https://openalex.org/W2160010046","https://openalex.org/W2527653927","https://openalex.org/W2768008485","https://openalex.org/W2792962047","https://openalex.org/W2899345358","https://openalex.org/W3000227939","https://openalex.org/W3090442715","https://openalex.org/W3130882026","https://openalex.org/W3142526730","https://openalex.org/W4206136496","https://openalex.org/W4286571821","https://openalex.org/W4288057941","https://openalex.org/W4312036228","https://openalex.org/W4360605377","https://openalex.org/W4360605801","https://openalex.org/W4360606251","https://openalex.org/W4376134112","https://openalex.org/W4387411165"],"related_works":["https://openalex.org/W2278942241","https://openalex.org/W2368405386","https://openalex.org/W1977749038","https://openalex.org/W2082979872","https://openalex.org/W1641489184","https://openalex.org/W3004044036","https://openalex.org/W2792167570","https://openalex.org/W2290076986","https://openalex.org/W4312326809","https://openalex.org/W2039630794"],"abstract_inverted_index":{"This":[0],"paper":[1],"introduces":[2],"a":[3,10,30,105,118,139],"dual":[4],"main":[5],"clock":[6],"generator":[7,39],"(DMCG)":[8],"and":[9,34,46,143,177,191],"digital":[11,64],"serializer":[12],"(DS)":[13],"to":[14,61,88,94,161],"improve":[15],"the":[16,20,42,48,52,63,74,90,96,122,136,153,162],"power":[17,75,155],"efficiency":[18],"of":[19,51,128,164,166,188],"time-interleaving":[21],"(TI)":[22],"analog-to-digital":[23],"converters":[24],"(ADCs).":[25],"The":[26,57,79,131],"proposed":[27,60],"DMCG":[28],"combines":[29],"dual-path":[31],"front":[32],"end":[33],"an":[35,126],"improved":[36],"selecting":[37,95],"signal":[38],"that":[40,135],"addresses":[41],"potential":[43],"phase":[44],"error":[45],"reduces":[47],"peak":[49],"current":[50],"clock-driving":[53],"circuits":[54],"by":[55,77,104],"60%.":[56],"DS":[58],"is":[59,86,157],"serialize":[62],"outputs":[65],"without":[66],"employing":[67],"power-hungry":[68],"inverter-based":[69],"buffer":[70],"chains":[71],"thus":[72],"reducing":[73],"consumption":[76,156],"39.2%.":[78],"reference-free":[80],"time":[81],"skew":[82],"extraction":[83],"algorithm":[84],"(RFA)":[85],"presented":[87],"mitigate":[89],"accuracy":[91],"deterioration":[92],"due":[93],"fixed":[97],"middle":[98],"channel.":[99],"These":[100],"techniques":[101],"are":[102],"validated":[103],"prototype":[106,123],"12-bit":[107],"10-GS/s":[108],"TI":[109],"pipelined":[110],"successive":[111],"approximation":[112],"register":[113],"(TI-Pi-SAR)":[114],"ADC.":[115],"Fabricated":[116],"in":[117],"28-nm":[119],"CMOS":[120],"process,":[121],"chip":[124],"occupies":[125],"area":[127],"4.4":[129],"mm2.":[130],"measurement":[132],"results":[133],"show":[134],"ADC":[137],"achieves":[138],"49.8":[140],"dB":[141,145,190],"SNDR":[142],"60.0":[144],"SFDR":[146],"after":[147],"calibration":[148],"at":[149],"Nyquist":[150],"frequency,":[151],"while":[152],"total":[154],"270":[158],"mW,":[159],"leading":[160],"figure":[163],"merits":[165],"Schreier":[167],"(FoM":[168,179],"<inline-formula":[169,180],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[170,181],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[171,182],"<tex-math":[172,183],"notation=\"LaTeX\">$_{\\mathrm":[173,184],"{S}}$":[174],"</tex-math></inline-formula>":[175,186],")":[176,187],"Walden":[178],"{W}}$":[185],"152.5":[189],"106.9":[192],"fJ/conv.-step,":[193],"respectively.":[194]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
