{"id":"https://openalex.org/W4386824975","doi":"https://doi.org/10.1109/tcsi.2023.3312817","title":"Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion","display_name":"Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion","publication_year":2023,"publication_date":"2023-09-18","ids":{"openalex":"https://openalex.org/W4386824975","doi":"https://doi.org/10.1109/tcsi.2023.3312817"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2023.3312817","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3312817","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5062261926","display_name":"Xi Meng","orcid":"https://orcid.org/0000-0002-2320-5012"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":true,"raw_author_name":"Xi Meng","raw_affiliation_strings":["Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100327750","display_name":"Haoran Li","orcid":"https://orcid.org/0009-0004-3833-4564"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Haoran Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051366940","display_name":"Peng Chen","orcid":"https://orcid.org/0000-0002-2872-9421"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Peng Chen","raw_affiliation_strings":["State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","Infineon Technologies, Cork, Ireland"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Infineon Technologies, Cork, Ireland","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006541988","display_name":"Jun Yin","orcid":"https://orcid.org/0000-0002-4195-4551"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Jun Yin","raw_affiliation_strings":["Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]},{"id":"https://openalex.org/I4210119392","display_name":"Institute of Microelectronics","ror":"https://ror.org/02s6gs133","country_code":"CN","type":"facility","lineage":["https://openalex.org/I19820366","https://openalex.org/I4210119392"]}],"countries":["CN","MO"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering (ECE), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I4210119392","https://openalex.org/I204512498"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5062261926"],"corresponding_institution_ids":["https://openalex.org/I204512498","https://openalex.org/I4210119392"],"apc_list":null,"apc_paid":null,"fwci":1.4337,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.81878464,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":"70","issue":"12","first_page":"5110","last_page":"5123"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10099","display_name":"GaN-based semiconductor devices and materials","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/3104","display_name":"Condensed Matter Physics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/inverse","display_name":"Inverse","score":0.6034303307533264},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.4757523238658905},{"id":"https://openalex.org/keywords/prime","display_name":"Prime (order theory)","score":0.42312371730804443},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3626222014427185},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.17167559266090393}],"concepts":[{"id":"https://openalex.org/C207467116","wikidata":"https://www.wikidata.org/wiki/Q4385666","display_name":"Inverse","level":2,"score":0.6034303307533264},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.4757523238658905},{"id":"https://openalex.org/C184992742","wikidata":"https://www.wikidata.org/wiki/Q7243229","display_name":"Prime (order theory)","level":2,"score":0.42312371730804443},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3626222014427185},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.17167559266090393},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2023.3312817","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3312817","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":54,"referenced_works":["https://openalex.org/W1500763588","https://openalex.org/W1966187371","https://openalex.org/W2031289928","https://openalex.org/W2033731278","https://openalex.org/W2034195195","https://openalex.org/W2098907338","https://openalex.org/W2099064239","https://openalex.org/W2104340505","https://openalex.org/W2141749418","https://openalex.org/W2152050858","https://openalex.org/W2169735823","https://openalex.org/W2245731133","https://openalex.org/W2321859177","https://openalex.org/W2326419276","https://openalex.org/W2521349449","https://openalex.org/W2543636785","https://openalex.org/W2588789014","https://openalex.org/W2596943636","https://openalex.org/W2625708510","https://openalex.org/W2792383978","https://openalex.org/W2795672079","https://openalex.org/W2800076889","https://openalex.org/W2802479922","https://openalex.org/W2886813860","https://openalex.org/W2890905903","https://openalex.org/W2891924334","https://openalex.org/W2899938501","https://openalex.org/W2913796664","https://openalex.org/W2921310211","https://openalex.org/W2922297820","https://openalex.org/W2946033997","https://openalex.org/W2971786152","https://openalex.org/W2972211361","https://openalex.org/W3007758149","https://openalex.org/W3015593006","https://openalex.org/W3023231518","https://openalex.org/W3028280451","https://openalex.org/W3047772528","https://openalex.org/W3049667933","https://openalex.org/W3091827235","https://openalex.org/W3111607930","https://openalex.org/W3134319786","https://openalex.org/W3184426925","https://openalex.org/W3194913244","https://openalex.org/W3201131231","https://openalex.org/W3210093361","https://openalex.org/W3215526671","https://openalex.org/W4200566763","https://openalex.org/W4225976526","https://openalex.org/W4226257562","https://openalex.org/W4285294152","https://openalex.org/W4300850987","https://openalex.org/W4312036229","https://openalex.org/W6781532476"],"related_works":["https://openalex.org/W1979597421","https://openalex.org/W2007980826","https://openalex.org/W4245490552","https://openalex.org/W4225152035","https://openalex.org/W2061531152","https://openalex.org/W3002753104","https://openalex.org/W2077600819","https://openalex.org/W1587224694","https://openalex.org/W2911598644","https://openalex.org/W2042127053"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,67,72,77,115,123,153,166,170,186,197,204,217,255],"theory":[4],"and":[5,50,79,120,159,163,231],"implementation":[6],"of":[7,108,117,157,168,235],"a":[8,134,147,210,233],"balanced":[9,148,218],"dual-core":[10,135,219],"inverse-class-F":[11],"(class-F":[12],"<inline-formula":[13,26,37,52,82,137,172,188,221,236],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[14,27,38,53,83,138,173,189,222,237],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[15,28,39,54,84,139,174,190,223,238],"<tex-math":[16,29,40,55,85,140,175,191,224,239],"notation=\"LaTeX\">$^{\\mathrm{":[17,30,56,141,176,192,225],"-1}}$":[18,31,142,193,226],"</tex-math></inline-formula>":[19,32,42,58,87,143,178,194,227,241],")":[20,43],"voltage-controlled":[21],"oscillator":[22],"(VCO).":[23],"The":[24,106],"class-F":[25,136,187,220],"topology":[33,200],"supports":[34],"high-quality-factor":[35],"(high-":[36],"notation=\"LaTeX\">$Q$":[41],"differential":[44,182,205],"switched-capacitors":[45],"(SCs)":[46],"for":[47,65],"both":[48],"fundamental":[49],"2":[51,171],"nd}}$":[57,177],"-harmonic":[59,179],"frequency":[60,180],"tuning,":[61],"which":[62],"is":[63,111],"beneficial":[64],"improving":[66,203],"phase":[68],"noise":[69,98,155],"(PN).":[70],"However,":[71],"unequal":[73],"parasitic":[74],"capacitors":[75],"from":[76,246,251,265],"NMOS":[78,158],"PMOS":[80,160],"negative":[81],"notation=\"LaTeX\">${g}$":[86],"textsubscript":[88],"m":[89],"transistors":[90,161],"make":[91],"it":[92],"impossible":[93],"to":[94,151,253,267],"minimize":[95,152],"their":[96],"flicker":[97,154],"upconversions":[99,156],"simultaneously,":[100],"especially":[101],"at":[102,243,262],"high":[103],"operating":[104],"frequencies.":[105],"mechanism":[107],"this":[109,130],"effect":[110],"analyzed":[112],"qualitatively":[113],"with":[114,181],"model":[116],"coupled":[118],"oscillators":[119],"verified":[121],"using":[122],"impulse-sensitivity":[124],"function":[125],"(ISF)":[126],"approach.":[127],"To":[128],"address":[129],"issue,":[131],"we":[132],"propose":[133],"VCO":[144,228,257],"that":[145],"leverages":[146],"coupling":[149],"scheme":[150],"simultaneously":[162],"still":[164],"keep":[165],"advantage":[167],"tuning":[169],"SCs":[183],"offered":[184],"by":[185],"topology.":[195],"Additionally,":[196],"symmetrical":[198],"circuit":[199],"aids":[201],"in":[202,209],"output":[206],"balancing.":[207],"Prototyped":[208],"28-nm":[211],"CMOS":[212],"process":[213],"without":[214],"ultra-thick":[215],"metal,":[216],"dissipates":[229],"19.7-mW":[230],"achieves":[232],"PN":[234],"notation=\"LaTeX\">$\\!-\\!113.9/\\!-\\!135.8$":[240],"-dBc/Hz":[242],"1/10-MHz":[244,263],"offset":[245,264],"an":[247],"18.23-GHz":[248],"carrier.":[249],"Tuned":[250],"15.22":[252],"18.23-GHz,":[254],"proposed":[256],"exhibits":[258],"superior":[259],"figure-of-merits":[260],"(FoMs)":[261],"185.3/187.0":[266],"186.2/188.1-dBc/Hz.":[268]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}