{"id":"https://openalex.org/W4386473364","doi":"https://doi.org/10.1109/tcsi.2023.3307611","title":"CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop","display_name":"CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop","publication_year":2023,"publication_date":"2023-09-06","ids":{"openalex":"https://openalex.org/W4386473364","doi":"https://doi.org/10.1109/tcsi.2023.3307611"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2023.3307611","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3307611","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026686667","display_name":"Geonhwi Lee","orcid":"https://orcid.org/0000-0002-6612-6584"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Geonhwi Lee","raw_affiliation_strings":["Department of Semiconductor Display Engineering, Sungkyunkwan University, Suwon-si, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Display Engineering, Sungkyunkwan University, Suwon-si, South Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076406424","display_name":"Bomin Joo","orcid":"https://orcid.org/0000-0001-5763-4272"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Bomin Joo","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012892234","display_name":"Bai\u2010Sun Kong","orcid":"https://orcid.org/0000-0002-1077-7038"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Bai-Sun Kong","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5026686667"],"corresponding_institution_ids":["https://openalex.org/I848706"],"apc_list":null,"apc_paid":null,"fwci":1.7999,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.84239403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":"70","issue":"12","first_page":"5316","last_page":"5327"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.798147439956665},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.7221882939338684},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6918742060661316},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5633735060691833},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.4638412594795227},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.45837002992630005},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.44892215728759766},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.43188953399658203},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.43069538474082947},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.412496417760849},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.35268107056617737},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3463258147239685},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.322549968957901},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3058815598487854},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2148708999156952},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14469018578529358},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.09309864044189453}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.798147439956665},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.7221882939338684},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6918742060661316},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5633735060691833},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.4638412594795227},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.45837002992630005},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.44892215728759766},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.43188953399658203},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.43069538474082947},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.412496417760849},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.35268107056617737},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3463258147239685},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.322549968957901},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3058815598487854},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2148708999156952},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14469018578529358},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.09309864044189453},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2023.3307611","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3307611","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322202","display_name":"IC Design Education Center","ror":"https://ror.org/005v57z85"},{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":36,"referenced_works":["https://openalex.org/W1986431631","https://openalex.org/W1995665089","https://openalex.org/W1998591589","https://openalex.org/W2019198721","https://openalex.org/W2029743175","https://openalex.org/W2046103068","https://openalex.org/W2056378213","https://openalex.org/W2083087340","https://openalex.org/W2087698376","https://openalex.org/W2118214977","https://openalex.org/W2129173641","https://openalex.org/W2140707343","https://openalex.org/W2149252784","https://openalex.org/W2151254061","https://openalex.org/W2164002677","https://openalex.org/W2416799949","https://openalex.org/W2460704157","https://openalex.org/W2524950583","https://openalex.org/W2596636257","https://openalex.org/W2768475350","https://openalex.org/W2782282142","https://openalex.org/W2811071181","https://openalex.org/W2893484398","https://openalex.org/W2898386872","https://openalex.org/W2959455346","https://openalex.org/W2981057900","https://openalex.org/W2996765167","https://openalex.org/W3011344043","https://openalex.org/W3033238766","https://openalex.org/W3048431371","https://openalex.org/W3135298190","https://openalex.org/W3163408809","https://openalex.org/W3196491533","https://openalex.org/W4200023449","https://openalex.org/W4285218709","https://openalex.org/W4296079399"],"related_works":["https://openalex.org/W2474747038","https://openalex.org/W2337711143","https://openalex.org/W4386968318","https://openalex.org/W2137310043","https://openalex.org/W3006003651","https://openalex.org/W4313332229","https://openalex.org/W2495024767","https://openalex.org/W2040807843","https://openalex.org/W54763883","https://openalex.org/W2559451387"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,11,27,34,85],"high-speed":[4,28],"low-power":[5],"CMOS":[6,87,129],"synchronous":[7],"up/down":[8],"counter":[9,44,81],"with":[10],"novel":[12],"compact":[13,59],"toggle":[14,60],"flip-flop":[15,61],"is":[16,62,118],"proposed":[17,80,95],"to":[18,39,53,100,106,114,126],"achieve":[19],"energy-":[20],"and":[21,67,73],"area-efficient":[22],"speed":[23,102],"enhancement.":[24],"It":[25,109],"adopts":[26],"local":[29,50],"clock":[30,46,51],"generation":[31,52],"based":[32],"on":[33],"single":[35],"Manchester":[36],"carry":[37],"chain":[38],"improve":[40],"counting":[41],"speed.":[42],"The":[43],"embeds":[45],"gating":[47],"in":[48,84,120],"the":[49,71,94],"eliminate":[54],"redundant":[55],"power":[56,68],"consumption.":[57],"A":[58,78],"incorporated":[63],"for":[64],"device":[65],"count":[66],"reduction.":[69],"Both":[70],"up-":[72],"down-counting":[74],"capabilities":[75],"are":[76],"supported.":[77],"16-bit":[79],"was":[82],"fabricated":[83],"28-nm":[86],"process.":[88],"Performance":[89],"evaluation":[90],"results":[91],"indicate":[92],"that":[93,112],"counters":[96],"can":[97],"provide":[98],"up":[99,113],"55%":[101],"improvement":[103],"as":[104],"compared":[105,125],"conventional":[107,127],"designs.":[108],"also":[110],"indicates":[111],"28%":[115],"performance":[116],"gain":[117],"obtained":[119],"terms":[121],"of":[122],"power-delay":[123],"product":[124],"clock-gated":[128],"counters.":[130]},"counts_by_year":[{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":6},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
