{"id":"https://openalex.org/W4320713062","doi":"https://doi.org/10.1109/tcsi.2023.3244338","title":"A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro","display_name":"A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro","publication_year":2023,"publication_date":"2023-02-14","ids":{"openalex":"https://openalex.org/W4320713062","doi":"https://doi.org/10.1109/tcsi.2023.3244338"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2023.3244338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3244338","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011379172","display_name":"Jiahao Song","orcid":"https://orcid.org/0000-0001-6296-1905"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jiahao Song","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0001-6296-1905","affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066653944","display_name":"Xiyuan Tang","orcid":"https://orcid.org/0000-0003-2181-9042"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiyuan Tang","raw_affiliation_strings":["Center for Brain Inspired Chips, Institute for Artificial Intelligence, Beijing, China","MOE, School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0003-2181-9042","affiliations":[{"raw_affiliation_string":"Center for Brain Inspired Chips, Institute for Artificial Intelligence, Beijing, China","institution_ids":[]},{"raw_affiliation_string":"MOE, School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040563637","display_name":"Xin Qiao","orcid":"https://orcid.org/0000-0003-1438-2348"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xin Qiao","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0003-1438-2348","affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002438548","display_name":"Yuan Wang","orcid":"https://orcid.org/0000-0002-4951-4286"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuan Wang","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-4951-4286","affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002760019","display_name":"Runsheng Wang","orcid":"https://orcid.org/0000-0002-7514-0767"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Runsheng Wang","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":"https://orcid.org/0000-0002-7514-0767","affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5062886480","display_name":"Ru Huang","orcid":"https://orcid.org/0000-0002-8146-4821"},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Ru Huang","raw_affiliation_strings":["Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Key Laboratory of Microelectronic Devices and Circuits (MOE), School of Integrated Circuits, Peking University, Beijing, China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":3.4842,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.9319043,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":99},"biblio":{"volume":"70","issue":"5","first_page":"1835","last_page":"1845"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transpose","display_name":"Transpose","score":0.7666066884994507},{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.5850154757499695},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5693261027336121},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.49324339628219604},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4915681779384613},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47152814269065857},{"id":"https://openalex.org/keywords/encoder","display_name":"Encoder","score":0.4134533405303955},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3900696337223053},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.38699623942375183},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3826923668384552},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.1818961501121521},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18050876259803772},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.16138461232185364},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15990838408470154},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1149287223815918}],"concepts":[{"id":"https://openalex.org/C200106649","wikidata":"https://www.wikidata.org/wiki/Q223683","display_name":"Transpose","level":3,"score":0.7666066884994507},{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.5850154757499695},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5693261027336121},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.49324339628219604},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4915681779384613},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47152814269065857},{"id":"https://openalex.org/C118505674","wikidata":"https://www.wikidata.org/wiki/Q42586063","display_name":"Encoder","level":2,"score":0.4134533405303955},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3900696337223053},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.38699623942375183},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3826923668384552},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.1818961501121521},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18050876259803772},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.16138461232185364},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15990838408470154},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1149287223815918},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C158693339","wikidata":"https://www.wikidata.org/wiki/Q190524","display_name":"Eigenvalues and eigenvectors","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2023.3244338","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2023.3244338","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[{"id":"https://openalex.org/G4602899521","display_name":null,"funder_award_id":"2020YFB2205502","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"},{"id":"https://openalex.org/G6847781164","display_name":null,"funder_award_id":"B18001","funder_id":"https://openalex.org/F4320327912","funder_display_name":"Higher Education Discipline Innovation Project"},{"id":"https://openalex.org/G927165947","display_name":null,"funder_award_id":"U20A20204","funder_id":"https://openalex.org/F4320321001","funder_display_name":"National Natural Science Foundation of China"}],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320327912","display_name":"Higher Education Discipline Innovation Project","ror":null},{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":56,"referenced_works":["https://openalex.org/W2300242332","https://openalex.org/W2591601611","https://openalex.org/W2782511028","https://openalex.org/W2787513570","https://openalex.org/W2792893539","https://openalex.org/W2899641901","https://openalex.org/W2920326572","https://openalex.org/W2921013323","https://openalex.org/W2943765373","https://openalex.org/W2966285227","https://openalex.org/W2969812992","https://openalex.org/W3000301330","https://openalex.org/W3010932008","https://openalex.org/W3015432327","https://openalex.org/W3016014942","https://openalex.org/W3016021860","https://openalex.org/W3017968097","https://openalex.org/W3026786299","https://openalex.org/W3099871312","https://openalex.org/W3133754064","https://openalex.org/W3134304371","https://openalex.org/W3134703406","https://openalex.org/W3134925155","https://openalex.org/W3135701542","https://openalex.org/W3135835558","https://openalex.org/W3135906938","https://openalex.org/W3139521791","https://openalex.org/W3163143851","https://openalex.org/W3163974534","https://openalex.org/W3164913974","https://openalex.org/W3180627186","https://openalex.org/W3183406752","https://openalex.org/W3184152611","https://openalex.org/W3184281067","https://openalex.org/W3185238080","https://openalex.org/W3185576717","https://openalex.org/W3205795241","https://openalex.org/W4200359890","https://openalex.org/W4214833843","https://openalex.org/W4220882094","https://openalex.org/W4220958508","https://openalex.org/W4220990849","https://openalex.org/W4221038786","https://openalex.org/W4226216109","https://openalex.org/W4280536295","https://openalex.org/W4280594598","https://openalex.org/W4280621230","https://openalex.org/W4285173196","https://openalex.org/W4288057953","https://openalex.org/W4312081866","https://openalex.org/W6748319235","https://openalex.org/W6776778896","https://openalex.org/W6791211223","https://openalex.org/W6791836880","https://openalex.org/W6805298817","https://openalex.org/W6809600860"],"related_works":["https://openalex.org/W2108719777","https://openalex.org/W2910771446","https://openalex.org/W2966758645","https://openalex.org/W2559054477","https://openalex.org/W2122693377","https://openalex.org/W2532170798","https://openalex.org/W4320854861","https://openalex.org/W3048955117","https://openalex.org/W2166656370","https://openalex.org/W4283787567"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,24,33,152,158],"compact,":[4],"robust,":[5],"and":[6,18,36,100,104,144,182],"transposable":[7],"SRAM":[8,64],"in-memory":[9],"computing":[10,45],"(IMC)":[11],"macro":[12,29,148,190],"to":[13,48,62,113],"support":[14,122],"feed":[15],"forward":[16],"(FF)":[17],"back":[19],"propagation":[20],"(BP)":[21],"computation":[22],"within":[23],"single":[25],"macro.":[26,237],"The":[27,54,107,146,189],"transpose":[28,235],"is":[30,66,149,226],"created":[31],"with":[32,42,124,206],"clustering":[34,59],"structure,":[35],"eight":[37],"6T":[38,63],"bitcells":[39],"are":[40],"shared":[41],"one":[43],"charge-domain":[44,75],"unit":[46],"(CCU)":[47],"efficiently":[49],"deploy":[50],"the":[51,71,78,82,86,90,93,135,140,203,229,233],"DNNs":[52,123],"weights.":[53],"normalized":[55],"area":[56],"overhead":[57],"of":[58,81,162,232],"structure":[60],"compared":[61],"cell":[65],"only":[67],"0.37.":[68],"During":[69],"computation,":[70],"CCU":[72],"performs":[73],"robust":[74],"operations":[76],"on":[77],"parasitic":[79],"capacitances":[80],"local":[83],"bitlines":[84],"in":[85,151,171,185],"IMC":[87,236],"cluster.":[88],"In":[89],"FF":[91],"mode,":[92,181,187],"proposed":[94,147,234],"design":[95],"supports":[96],"128-input":[97],"1b":[98,101,108,159,207],"XNOR":[99],"AND":[102,109,180],"multiplications":[103],"accumulations":[105],"(MACs).":[106],"can":[110,121],"be":[111],"extended":[112],"multi-bit":[114],"MAC":[115],"via":[116],"bit-serial":[117],"(BS)":[118],"mapping,":[119],"which":[120],"various":[125],"precision.":[126],"A":[127],"power-gated":[128],"auto-zero":[129],"Flash":[130],"analog-to-digital":[131],"converter":[132],"(ADC)":[133],"reducing":[134],"input":[136],"offset":[137],"voltage":[138],"maintains":[139],"overall":[141],"energy":[142,160],"efficiency":[143,161],"throughput.":[145],"prototyped":[150],"28-nm":[153],"CMOS":[154],"process.":[155],"It":[156],"demonstrates":[157],"<inline-formula":[163,173,192,208],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[164,174,193,209],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[165,175,194,210],"<tex-math":[166,176,195,211],"notation=\"LaTeX\">$166\\vert":[167],"257$":[168],"</tex-math></inline-formula>":[169,179,199,214],"TOPS/W":[170,184],"FF-XNOR":[172],"notation=\"LaTeX\">$\\vert":[177,212],"$":[178],"31.8":[183],"BP":[186,230],"respectively.":[188],"achieves":[191],"notation=\"LaTeX\">$80.26\\%":[196],"\\vert":[197],"85.07\\%$":[198],"classification":[200,221],"accuracy":[201,222],"for":[202],"CIFAR-10":[204],"dataset":[205,220],"4\\text{b}$":[213],"CNN":[215],"models.":[216],"Besides,":[217],"95.50%":[218],"MNIST":[219],"(95.66%":[223],"software":[224],"accuracy)":[225],"achieved":[227],"by":[228],"mode":[231]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":14},{"year":2023,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
