{"id":"https://openalex.org/W4225682136","doi":"https://doi.org/10.1109/tcsi.2022.3166550","title":"NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator","display_name":"NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator","publication_year":2022,"publication_date":"2022-04-27","ids":{"openalex":"https://openalex.org/W4225682136","doi":"https://doi.org/10.1109/tcsi.2022.3166550"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2022.3166550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2022.3166550","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006902322","display_name":"Rog\u00e9rio Paludo","orcid":"https://orcid.org/0000-0001-5554-7693"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Rogerio Paludo","raw_affiliation_strings":["INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077537777","display_name":"Leonel Sousa","orcid":"https://orcid.org/0000-0002-8066-221X"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Leonel Sousa","raw_affiliation_strings":["INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"INESC-ID, Instituto Superior T&#x00E9;cnico, Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5006902322"],"corresponding_institution_ids":["https://openalex.org/I121345201","https://openalex.org/I141596103"],"apc_list":null,"apc_paid":null,"fwci":13.0385,"has_fulltext":false,"cited_by_count":44,"citation_normalized_percentile":{"value":0.98753543,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":97,"max":100},"biblio":{"volume":"69","issue":"7","first_page":"2669","last_page":"2682"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10237","display_name":"Cryptography and Data Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7011710405349731},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6596927642822266},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.648817777633667},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4855906367301941},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.43266960978507996},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.4315710961818695},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4239642918109894},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42339447140693665},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.41962775588035583},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.27076542377471924},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.22612091898918152},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.20552924275398254},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11121195554733276}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7011710405349731},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6596927642822266},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.648817777633667},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4855906367301941},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.43266960978507996},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.4315710961818695},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4239642918109894},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42339447140693665},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.41962775588035583},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.27076542377471924},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.22612091898918152},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.20552924275398254},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11121195554733276}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2022.3166550","is_oa":false,"landing_page_url":"https://doi.org/10.1109/tcsi.2022.3166550","pdf_url":null,"source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G2441341484","display_name":null,"funder_award_id":"UIDB/50021/2020","funder_id":"https://openalex.org/F4320334779","funder_display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia"}],"funders":[{"id":"https://openalex.org/F4320334779","display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","ror":"https://ror.org/00snfqn58"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":54,"referenced_works":["https://openalex.org/W150223756","https://openalex.org/W913176383","https://openalex.org/W1996217612","https://openalex.org/W2031533839","https://openalex.org/W2061171222","https://openalex.org/W2067507719","https://openalex.org/W2069441027","https://openalex.org/W2090394116","https://openalex.org/W2102182691","https://openalex.org/W2141685778","https://openalex.org/W2167110608","https://openalex.org/W2168353136","https://openalex.org/W2293449522","https://openalex.org/W2467320551","https://openalex.org/W2527617455","https://openalex.org/W2537286916","https://openalex.org/W2759027818","https://openalex.org/W2768174108","https://openalex.org/W2773773675","https://openalex.org/W2792565434","https://openalex.org/W2885339274","https://openalex.org/W2921423584","https://openalex.org/W2934510082","https://openalex.org/W2936567838","https://openalex.org/W2942255051","https://openalex.org/W2952334088","https://openalex.org/W2979557494","https://openalex.org/W2981801946","https://openalex.org/W2995995168","https://openalex.org/W3012235108","https://openalex.org/W3013093367","https://openalex.org/W3016085798","https://openalex.org/W3019884349","https://openalex.org/W3021991761","https://openalex.org/W3036297911","https://openalex.org/W3065439923","https://openalex.org/W3093786062","https://openalex.org/W3133594818","https://openalex.org/W3155680838","https://openalex.org/W3176372658","https://openalex.org/W3195910278","https://openalex.org/W3196234312","https://openalex.org/W3202423328","https://openalex.org/W3205370276","https://openalex.org/W3211431797","https://openalex.org/W4200628863","https://openalex.org/W4231090573","https://openalex.org/W4240021066","https://openalex.org/W4246219036","https://openalex.org/W4250492047","https://openalex.org/W6606067566","https://openalex.org/W6760526656","https://openalex.org/W6802233522","https://openalex.org/W7000941529"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W1493975478","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W1485756991","https://openalex.org/W2749962643","https://openalex.org/W2376218453"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"two":[3],"architectures":[4,66],"for":[5,26,44,94],"the":[6,64,92,105,131,134,144,161,164,167,177,181,192],"acceleration":[7,96],"of":[8,63,99,107,125,133,163,180,194],"Number":[9],"Theoretic":[10],"Transforms":[11],"(NTTs)":[12],"using":[13],"a":[14,21,37,50,70,123],"novel":[15],"Montgomery-based":[16],"butterfly.":[17],"We":[18],"first":[19],"design":[20],"custom":[22,59,95],"NTT":[23],"hardware":[24],"accelerator":[25],"Field-Programmable":[27],"Gate":[28],"Arrays":[29],"(FPGAs).":[30],"The":[31,61,136],"butterfly":[32],"architecture":[33,146],"is":[34,56,67,147],"expanded":[35],"to":[36,160],"Modular":[38],"Arithmetic":[39],"Logic":[40],"Unit":[41],"(MALU)":[42],"and":[43,47,74,102,111,116,151,155],"greater":[45],"reuse":[46],"easier":[48],"programmability":[49],"six-stage":[51],"pipeline":[52],"Linux-ready":[53],"RISC-V":[54,183],"core":[55,184],"extended":[57,182],"with":[58,75,130],"instructions.":[60],"performance":[62],"proposed":[65,145,168],"assessed":[68],"on":[69,81],"Xilinx":[71],"Ultrascale+":[72],"FPGA":[73],"an":[76,172],"Application-Specific":[77],"Integrated":[78],"Circuit":[79],"(ASIC)":[80],"<inline-formula":[82],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[83],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[84],"<tex-math":[85],"notation=\"LaTeX\">$28{n}\\text{m}$":[86],"</tex-math></inline-formula>":[87],"CMOS":[88],"technology.":[89],"In":[90],"FPGA,":[91],"results":[93,138],"show":[97,139],"reductions":[98],"30%,":[100],"90%":[101],"42%":[103],"in":[104,128,148,191],"number":[106],"Lookup":[108],"tables":[109],"(LUTs)":[110],"registers,":[112],"Block":[113],"RAMs":[114],"(BRAMs)":[115],"Digital":[117],"Signal":[118],"Processors":[119],"(DSPs),":[120],"while":[121],"providing":[122],"speedup":[124],"1.9":[126],"times,":[127],"comparison":[129],"state":[132,162],"art.":[135,165],"ASIC":[137],"that":[140],"at":[141],"1":[142],"GHz":[143],"average":[149],"45%":[150],"52%":[152],"less":[153],"area":[154,179],"power":[156],"hungry,":[157],"respectively,":[158],"compared":[159],"Furthermore,":[166],"MALU,":[169],"operating":[170],"as":[171],"additional":[173],"execution":[174],"unit,":[175],"increases":[176],"overall":[178],"by":[185],"only":[186],"10%,":[187],"without":[188],"significant":[189],"changes":[190],"frequency":[193],"operation.":[195]},"counts_by_year":[{"year":2026,"cited_by_count":3},{"year":2025,"cited_by_count":9},{"year":2024,"cited_by_count":15},{"year":2023,"cited_by_count":12},{"year":2022,"cited_by_count":5}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
