{"id":"https://openalex.org/W3198434218","doi":"https://doi.org/10.1109/tcsi.2021.3105451","title":"Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS","display_name":"Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS","publication_year":2021,"publication_date":"2021-08-27","ids":{"openalex":"https://openalex.org/W3198434218","doi":"https://doi.org/10.1109/tcsi.2021.3105451","mag":"3198434218"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2021.3105451","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3105451","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9684154/09524358.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/8919/9684154/09524358.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051366940","display_name":"Peng Chen","orcid":"https://orcid.org/0000-0002-2872-9421"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["IE","MO"],"is_corresponding":true,"raw_author_name":"Peng Chen","raw_affiliation_strings":["University College Dublin, Dublin 4, Ireland","University of Macau, Macau, China","Wuxi GrandMicro, Wuxi, China"],"raw_orcid":"https://orcid.org/0000-0002-2872-9421","affiliations":[{"raw_affiliation_string":"University College Dublin, Dublin 4, Ireland","institution_ids":["https://openalex.org/I100930933"]},{"raw_affiliation_string":"University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Wuxi GrandMicro, Wuxi, China","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006541988","display_name":"Jun Yin","orcid":"https://orcid.org/0000-0002-4195-4551"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Jun Yin","raw_affiliation_strings":["Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-4195-4551","affiliations":[{"raw_affiliation_string":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035373707","display_name":"Feifei Zhang","orcid":"https://orcid.org/0000-0002-9862-6671"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]},{"id":"https://openalex.org/I4210123126","display_name":"Silicon Austria Labs (Austria)","ror":"https://ror.org/03b1qgn79","country_code":"AT","type":"company","lineage":["https://openalex.org/I4210123126"]}],"countries":["AT","IE"],"is_corresponding":false,"raw_author_name":"Feifei Zhang","raw_affiliation_strings":["School of Electrical and Electronic Engineering, University College Dublin, Dublin D4, Ireland","Silicon Austria Labs, Linz, Austria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin D4, Ireland","institution_ids":["https://openalex.org/I100930933"]},{"raw_affiliation_string":"Silicon Austria Labs, Linz, Austria","institution_ids":["https://openalex.org/I4210123126"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058845450","display_name":"Pui\u2010In Mak","orcid":"https://orcid.org/0000-0002-3579-8740"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Pui-In Mak","raw_affiliation_strings":["Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China"],"raw_orcid":"https://orcid.org/0000-0002-3579-8740","affiliations":[{"raw_affiliation_string":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]},{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO","PT"],"is_corresponding":false,"raw_author_name":"Rui P. Martins","raw_affiliation_strings":["Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisboa, Portugal"],"raw_orcid":"https://orcid.org/0000-0003-2821-648X","affiliations":[{"raw_affiliation_string":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Faculty of Science and Technology, University of Macau, Macau, China","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, Lisboa, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027017637","display_name":"Robert Bogdan Staszewski","orcid":"https://orcid.org/0000-0001-9848-1129"},"institutions":[{"id":"https://openalex.org/I100930933","display_name":"University College Dublin","ror":"https://ror.org/05m7pjf47","country_code":"IE","type":"education","lineage":["https://openalex.org/I100930933"]},{"id":"https://openalex.org/I686019","display_name":"AGH University of Krakow","ror":"https://ror.org/00bas1c41","country_code":"PL","type":"education","lineage":["https://openalex.org/I686019"]}],"countries":["IE","PL"],"is_corresponding":false,"raw_author_name":"Robert Bogdan Staszewski","raw_affiliation_strings":["Department of Measurement and Instrumentation, University of Science and Technology, Krakow, Poland","School of Electrical and Electronic Engineering, University College Dublin, Dublin D4, Ireland"],"raw_orcid":"https://orcid.org/0000-0001-9848-1129","affiliations":[{"raw_affiliation_string":"Department of Measurement and Instrumentation, University of Science and Technology, Krakow, Poland","institution_ids":["https://openalex.org/I686019"]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, University College Dublin, Dublin D4, Ireland","institution_ids":["https://openalex.org/I100930933"]}]}],"institutions":[],"countries_distinct_count":5,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5051366940"],"corresponding_institution_ids":["https://openalex.org/I100930933","https://openalex.org/I204512498"],"apc_list":null,"apc_paid":null,"fwci":1.2201,"has_fulltext":true,"cited_by_count":14,"citation_normalized_percentile":{"value":0.78999941,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":"69","issue":"1","first_page":"196","last_page":"206"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7332375645637512},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.6177982091903687},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.5603699088096619},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5288052558898926},{"id":"https://openalex.org/keywords/integral-nonlinearity","display_name":"Integral nonlinearity","score":0.5285027623176575},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.4730460047721863},{"id":"https://openalex.org/keywords/nonlinear-system","display_name":"Nonlinear system","score":0.44567441940307617},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.43451496958732605},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.42076951265335083},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4203193485736847},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3459392488002777},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.3129194378852844},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.20207050442695618},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18000638484954834},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15568098425865173},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.11176955699920654},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.10753539204597473}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7332375645637512},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.6177982091903687},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.5603699088096619},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5288052558898926},{"id":"https://openalex.org/C130829357","wikidata":"https://www.wikidata.org/wiki/Q1665386","display_name":"Integral nonlinearity","level":4,"score":0.5285027623176575},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.4730460047721863},{"id":"https://openalex.org/C158622935","wikidata":"https://www.wikidata.org/wiki/Q660848","display_name":"Nonlinear system","level":2,"score":0.44567441940307617},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.43451496958732605},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.42076951265335083},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4203193485736847},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3459392488002777},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.3129194378852844},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.20207050442695618},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18000638484954834},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15568098425865173},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.11176955699920654},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.10753539204597473},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2021.3105451","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3105451","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9684154/09524358.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tcsi.2021.3105451","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3105451","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9684154/09524358.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[{"id":"https://openalex.org/G3678921673","display_name":null,"funder_award_id":"MYRG2018-00220-AMSV","funder_id":"https://openalex.org/F4320322841","funder_display_name":"Universidade de Macau"},{"id":"https://openalex.org/G5906654117","display_name":null,"funder_award_id":"14/RP/I2921","funder_id":"https://openalex.org/F4320320847","funder_display_name":"Science Foundation Ireland"}],"funders":[{"id":"https://openalex.org/F4320320847","display_name":"Science Foundation Ireland","ror":"https://ror.org/0271asj38"},{"id":"https://openalex.org/F4320321884","display_name":"Shanxi Scholarship Council of China","ror":"https://ror.org/04atp4p48"},{"id":"https://openalex.org/F4320322841","display_name":"Universidade de Macau","ror":"https://ror.org/01r4q9n85"}],"has_content":{"grobid_xml":true,"pdf":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3198434218.pdf","grobid_xml":"https://content.openalex.org/works/W3198434218.grobid-xml"},"referenced_works_count":35,"referenced_works":["https://openalex.org/W1567828147","https://openalex.org/W1713446188","https://openalex.org/W1775840686","https://openalex.org/W1940483669","https://openalex.org/W1979229036","https://openalex.org/W2028941857","https://openalex.org/W2036880312","https://openalex.org/W2056492926","https://openalex.org/W2062952706","https://openalex.org/W2065992070","https://openalex.org/W2072864093","https://openalex.org/W2079608392","https://openalex.org/W2112731410","https://openalex.org/W2120500930","https://openalex.org/W2152144298","https://openalex.org/W2161066961","https://openalex.org/W2163630970","https://openalex.org/W2169047810","https://openalex.org/W2172107008","https://openalex.org/W2177833654","https://openalex.org/W2195134145","https://openalex.org/W2291658330","https://openalex.org/W2397557477","https://openalex.org/W2516199239","https://openalex.org/W2559073178","https://openalex.org/W2611384543","https://openalex.org/W2771032687","https://openalex.org/W2792016068","https://openalex.org/W2888480449","https://openalex.org/W2896178319","https://openalex.org/W2899818391","https://openalex.org/W2908054846","https://openalex.org/W2959661790","https://openalex.org/W2975185022","https://openalex.org/W3042749491"],"related_works":["https://openalex.org/W2474043983","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W2544336511","https://openalex.org/W2144737022","https://openalex.org/W2000633969","https://openalex.org/W1978186604","https://openalex.org/W1991465945","https://openalex.org/W2364492267","https://openalex.org/W2370818752"],"abstract_inverted_index":{"Nonlinearity":[0],"of":[1,25,44,114],"a":[2,41,116,138],"digital-to-time":[3],"converter":[4,34],"(DTC)":[5],"is":[6,47,129],"pivotal":[7],"to":[8,49,83,142],"spur":[9,87],"performance":[10],"in":[11,54,95],"DTC-based":[12],"all-digital":[13],"phase-locked-loops":[14],"(ADPLL).":[15],"In":[16],"this":[17],"paper,":[18],"we":[19],"characterize":[20],"and":[21,63,81],"analyze":[22],"the":[23,51,57,84,90,96,103,119,144],"mismatch":[24],"cascaded-delay-unit":[26],"DTCs.":[27],"Through":[28],"an":[29],"improved":[30],"built-in-self-test":[31],"(BIST)":[32],"time-to-digital":[33],"(TDC)":[35],"assisted":[36],"with":[37,137],"phase-to-frequency":[38],"detector":[39],"(PFD),":[40],"measurement":[42],"system":[43,100,134,139],"sub-half-ps":[45],"accuracy":[46],"constructed":[48],"conduct":[50],"characterization.":[52],"Fabricated":[53],"28-nm":[55],"CMOS,":[56],"DTC":[58,91],"transfer":[59],"functions":[60],"are":[61,65,76],"measured,":[62],"mismatches":[64],"compared":[66,77],"against":[67,78],"Monte-Carlo":[68],"simulation":[69],"results.":[70],"The":[71,98,112,131],"integral":[72],"nonlinearity":[73],"(INL)":[74],"results":[75],"each":[79],"other":[80],"converted":[82],"in-band":[85],"fractional":[86],"level":[88],"when":[89],"would":[92],"be":[93],"deployed":[94],"ADPLL.":[97],"BIST-TDC":[99],"thus":[101],"characterizes":[102],"on-chip":[104],"delays":[105],"without":[106],"expensive":[107],"equipment":[108],"or":[109],"complex":[110],"setup.":[111],"effectiveness":[113],"adding":[115],"PFD":[117],"into":[118],"<inline-formula":[120],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[121],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">":[122],"<tex-math":[123],"notation=\"LaTeX\">$\\Delta":[124],"\\!\\Sigma":[125],"$":[126],"</tex-math></inline-formula>":[127],"loop":[128],"validated.":[130],"entire":[132],"BIST":[133],"consumes":[135],"0.6mW":[136],"self-calibration":[140],"algorithm":[141],"tackle":[143],"analog":[145],"blocks\u2019":[146],"nonlinearities.":[147]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":7},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":3}],"updated_date":"2026-03-27T05:58:40.876381","created_date":"2025-10-10T00:00:00"}
