{"id":"https://openalex.org/W3196249432","doi":"https://doi.org/10.1109/tcsi.2021.3102386","title":"Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures","display_name":"Real-Time Downsampling in Digital Storage Oscilloscopes With Multichannel Architectures","publication_year":2021,"publication_date":"2021-08-13","ids":{"openalex":"https://openalex.org/W3196249432","doi":"https://doi.org/10.1109/tcsi.2021.3102386","mag":"3196249432"},"language":"en","primary_location":{"id":"doi:10.1109/tcsi.2021.3102386","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3102386","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9551015/09513253.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"hybrid","oa_url":"https://ieeexplore.ieee.org/ielx7/8919/9551015/09513253.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050933189","display_name":"Ettore Napoli","orcid":"https://orcid.org/0000-0002-6200-3990"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Ettore Napoli","raw_affiliation_strings":["Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy"],"raw_orcid":"https://orcid.org/0000-0002-6200-3990","affiliations":[{"raw_affiliation_string":"Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090628870","display_name":"Efstratios Zacharelos","orcid":"https://orcid.org/0000-0002-7334-2250"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Efstratios Zacharelos","raw_affiliation_strings":["Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy"],"raw_orcid":"https://orcid.org/0000-0002-7334-2250","affiliations":[{"raw_affiliation_string":"Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006659544","display_name":"Mauro D\u2019Arco","orcid":"https://orcid.org/0000-0003-1641-8359"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro D\u2019Arco","raw_affiliation_strings":["Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy"],"raw_orcid":"https://orcid.org/0000-0003-1641-8359","affiliations":[{"raw_affiliation_string":"Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy","institution_ids":["https://openalex.org/I71267560"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058182656","display_name":"A.G.M. Strollo","orcid":"https://orcid.org/0000-0001-5737-1783"},"institutions":[{"id":"https://openalex.org/I71267560","display_name":"University of Naples Federico II","ror":"https://ror.org/05290cv24","country_code":"IT","type":"education","lineage":["https://openalex.org/I71267560"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Giuseppe Maria Strollo","raw_affiliation_strings":["Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy"],"raw_orcid":"https://orcid.org/0000-0001-5737-1783","affiliations":[{"raw_affiliation_string":"Department of Electrical and Information Technology Engineering, University of Napoli Federico II, Naples, Italy","institution_ids":["https://openalex.org/I71267560"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I71267560"],"apc_list":null,"apc_paid":null,"fwci":0.4358,"has_fulltext":true,"cited_by_count":7,"citation_normalized_percentile":{"value":0.53952748,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"68","issue":"10","first_page":"4142","last_page":"4155"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7419636845588684},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5151183009147644},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.5144572257995605},{"id":"https://openalex.org/keywords/oscilloscope","display_name":"Oscilloscope","score":0.49231088161468506},{"id":"https://openalex.org/keywords/upsampling","display_name":"Upsampling","score":0.45467644929885864},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.4467405676841736},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.4133259057998657},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.41283249855041504},{"id":"https://openalex.org/keywords/decimation","display_name":"Decimation","score":0.41060441732406616},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38239794969558716},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.3447762131690979},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.19883829355239868},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14449629187583923},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.10177290439605713}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7419636845588684},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5151183009147644},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.5144572257995605},{"id":"https://openalex.org/C184026988","wikidata":"https://www.wikidata.org/wiki/Q174320","display_name":"Oscilloscope","level":3,"score":0.49231088161468506},{"id":"https://openalex.org/C110384440","wikidata":"https://www.wikidata.org/wiki/Q1143270","display_name":"Upsampling","level":3,"score":0.45467644929885864},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.4467405676841736},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.4133259057998657},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.41283249855041504},{"id":"https://openalex.org/C173642442","wikidata":"https://www.wikidata.org/wiki/Q1253346","display_name":"Decimation","level":3,"score":0.41060441732406616},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38239794969558716},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.3447762131690979},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.19883829355239868},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14449629187583923},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.10177290439605713},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/tcsi.2021.3102386","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3102386","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9551015/09513253.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"}],"best_oa_location":{"id":"doi:10.1109/tcsi.2021.3102386","is_oa":true,"landing_page_url":"https://doi.org/10.1109/tcsi.2021.3102386","pdf_url":"https://ieeexplore.ieee.org/ielx7/8919/9551015/09513253.pdf","source":{"id":"https://openalex.org/S116977442","display_name":"IEEE Transactions on Circuits and Systems I Regular Papers","issn_l":"1549-8328","issn":["1549-8328","1558-0806"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Transactions on Circuits and Systems I: Regular Papers","raw_type":"journal-article"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W3196249432.pdf","grobid_xml":"https://content.openalex.org/works/W3196249432.grobid-xml"},"referenced_works_count":52,"referenced_works":["https://openalex.org/W1541305607","https://openalex.org/W1541939128","https://openalex.org/W1604540620","https://openalex.org/W1976695026","https://openalex.org/W2004178252","https://openalex.org/W2012349701","https://openalex.org/W2015348135","https://openalex.org/W2019310074","https://openalex.org/W2075420576","https://openalex.org/W2097764824","https://openalex.org/W2100922387","https://openalex.org/W2102746938","https://openalex.org/W2114885057","https://openalex.org/W2115617497","https://openalex.org/W2117767670","https://openalex.org/W2120736264","https://openalex.org/W2121486156","https://openalex.org/W2121843794","https://openalex.org/W2143218672","https://openalex.org/W2148053063","https://openalex.org/W2151617594","https://openalex.org/W2166860007","https://openalex.org/W2434129824","https://openalex.org/W2438715338","https://openalex.org/W2485456237","https://openalex.org/W2501245014","https://openalex.org/W2547302651","https://openalex.org/W2580715839","https://openalex.org/W2609552772","https://openalex.org/W2742372882","https://openalex.org/W2802476548","https://openalex.org/W2802993124","https://openalex.org/W2906404755","https://openalex.org/W2914078437","https://openalex.org/W2945563156","https://openalex.org/W2949285805","https://openalex.org/W2958428171","https://openalex.org/W2971397923","https://openalex.org/W2972355950","https://openalex.org/W2972781853","https://openalex.org/W2976506721","https://openalex.org/W2976882512","https://openalex.org/W2983271157","https://openalex.org/W3010802287","https://openalex.org/W3012567720","https://openalex.org/W3029206269","https://openalex.org/W3032286445","https://openalex.org/W3196249432","https://openalex.org/W6675623753","https://openalex.org/W6677457685","https://openalex.org/W6678278850","https://openalex.org/W6775568232"],"related_works":["https://openalex.org/W1989627944","https://openalex.org/W4254353755","https://openalex.org/W2158391860","https://openalex.org/W2102662996","https://openalex.org/W2381117782","https://openalex.org/W3212642193","https://openalex.org/W2771062617","https://openalex.org/W2141592563","https://openalex.org/W2126613782","https://openalex.org/W2392174884"],"abstract_inverted_index":{"Digital":[0,22],"Storage":[1],"Oscilloscopes":[2],"(DSOs)":[3],"conjugate":[4],"high":[5],"performance":[6,154],"with":[7,29,151,169,181,184,194,205],"large":[8],"number":[9],"of":[10,90,112,198,209,215],"features":[11],"and":[12,25,35,38,46,76,119],"flexibility.":[13],"The":[14,79,106,143],"basic":[15],"structure,":[16],"based":[17,130],"on":[18,131],"fast":[19],"Analog":[20],"to":[21,147],"Converter":[23],"(ADC)":[24],"memory,":[26],"is":[27,57,145],"augmented":[28],"several":[30,63],"components":[31],"for":[32,62,139,163,178],"channel":[33],"matching":[34],"bandwidth":[36],"improvement,":[37],"processors":[39],"that":[40,61,72,86,134,156],"provide":[41],"visualization,":[42],"frequency":[43],"processing,":[44],"jitter":[45],"stability":[47],"measurement,":[48],"etc.":[49],"Unfortunately,":[50],"fine":[51,88],"resolution":[52],"in":[53,149,172,191],"sample":[54],"rate":[55,197],"selection":[56],"not":[58,123],"available,":[59],"such":[60],"applications":[64],"the":[65,91,97,140,152,188],"user":[66],"must":[67],"run":[68],"complex":[69],"measurement":[70],"procedures":[71],"require":[73],"data":[74,116],"download":[75],"offline":[77],"processing.":[78],"paper":[80],"proposes":[81],"a":[82,110,158,195,206,212],"dedicated":[83],"digital":[84],"circuit":[85,108,144,164,189],"offers":[87],"control":[89],"time-base":[92],"by":[93,125],"real":[94,192],"time":[95,193],"downsampling":[96],"input":[98,186],"stream":[99],"at":[100,202],"an":[101,179],"almost":[102],"arbitrary":[103],"sampling":[104,141,196],"rate.":[105,142],"proposed":[107],"implements":[109],"series":[111],"operations":[113],"involving":[114],"real-time":[115],"filtering,":[117],"defragmentation":[118],"packing,":[120],"which":[121],"are":[122,166],"considered":[124],"alternative":[126],"approaches,":[127],"like":[128],"those":[129],"polyphase":[132],"filters,":[133],"offer":[135],"very":[136],"limited":[137],"choices":[138],"designed":[146,177],"work":[148],"conjunction":[150],"highest":[153],"DSOs":[155],"use":[157],"multichannel":[159],"architecture.":[160],"Design":[161],"rules":[162],"design":[165],"provided":[167],"together":[168],"implementation":[170],"results":[171],"14nm":[173],"FinFET":[174],"technology.":[175],"When":[176],"architecture":[180],"64":[182],"channels":[183],"8bit":[185],"samples":[187],"works":[190],"220":[199],"GSps":[200],"running":[201],"3.42":[203],"GHz,":[204],"silicon":[207],"footprint":[208],"0.17":[210],"mm2and":[211],"power":[213],"dissipation":[214],"0.85W.":[216]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":3}],"updated_date":"2026-07-29T09:40:50.615796","created_date":"2025-10-10T00:00:00"}